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2020-08-07xive/p9: Enforce thread enablement before TIMA accessesCédric Le Goater1-0/+15
To activate the HW thread context ring, and its associated thread interrupt registers, a thread needs to raise the VT bit in word2. This requires access to the TIMA and this access is only granted if the thread was first enabled at the XIVE IC level. This is done in a sequence in xive_cpu_callin() but there is a chance that the accesses done on the TIMA do not see the update of the enable register. To make sure that the enablement has completed, add an extra load on the PC_THREAD_EN_REGx register. This guarantees that the TIMA accesses will see the latest state of the enable register. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-08-07doc: Document more platformsJoel Stanley1-1/+4
These platforms are supported in the tree but didn't make it to the docs folder yet. Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-08-07Fix typos in commentGustavo Romero1-2/+2
Fix two typos in comment describing a member of 'platform' struct. Signed-off-by: Gustavo Romero <gromero@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-08-07hdata: Add new "smp-cable-connector" VPD keywordKlaus Heinrich Kiwi1-0/+1
Recent FSP versions are defining a new VPD keyword 'SN' that brings SMP Cable Connector FRU info. Signed-off-by: Klaus Heinrich Kiwi <klaus@linux.vnet.ibm.com> Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-08-07Update comments for bit manipulation macrosGustavo Romero1-3/+3
Bit manipulation code was updated but comments related to it were not. This commit updates the comments for the main macros, GET/SETFIELD, to make them match the code. Signed-off-by: Gustavo Romero <gromero@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-08-07xive: Fix typos in commentsGustavo Romero1-2/+2
Fix a typo in comment about Presentation Controller Base Address Register and another typo about code to configure the queue overflows. Signed-off-by: Gustavo Romero <gromero@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-08-07hw/psi-p9: Configure IRQ offset before XIVE notifyOliver O'Halloran1-10/+10
When configuring the XIVE notification address any currently pending interrupts will be delivered once the the valid bit in the BAR is set. Currently we enable the notify BAR before we've configured the global interrupt number offset for the PSI interrupts. If any PSI interrupt is pending at this point we'll send an interrupt trigger notification for the wrong interrupt vector. This can potentially cause a checkstop since there may not be an EAS / IVT configure for that vector. Fix this by fixing the ordering so we setup the offset before the XIVE notification address. Cc: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-08-07hdata: Ensure the prd-label hbrt-code-image is prefixedOliver O'Halloran1-0/+9
Older versions of opal-prd (i.e. most of them shipped by distros) expect the HBRT image to have the PRD label of "ibm,hbrt-code-image". Commit c3bfa3209559 ("hdata: Fix reserved node label search") made opal-prd check for both strings, but since opal-prd itself is the only component interested in locating the hbrt-code-image we might as well just add the prefix in firmware. Cc: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-07-03skiboot v6.6.2 release notesVasant Hegde1-0/+17
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2020-07-02fsp: Skip sysdump retrieval only in MPIPL bootVasant Hegde1-3/+11
It seems we should continue to retrieval SYSDUMP except in MPIPL boot. Fixes: d6eb510 (fsp: Ignore platform dump notification on P9) Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-30xive: Fix two typos in commentsGustavo Romero1-2/+2
This commit fixes two typos in XIVE comments about how to handle an escalation event. Signed-off-by: Gustavo Romero <gromero@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-30prd: Do not assert if HBRT makes unsupported callVasant Hegde1-13/+29
There are few PRD function which are specific to FSP/BMC. If HBRT accidently makes those call we are asserting today.. which is not good. This function replaces those assert()'s with OPAL_UNSUPPORTED return value. Suggested-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-30mpipl: Move opal_mpipl_save_crashing_pir() call to platform specific codeVasant Hegde4-11/+8
Commit 34664746 moved opal_mpipl_save_crashing_pir() function call from platform specific code to generic assert() path. I completely missed to take care of all terminate path :-( This resulted in breaking `opalcore` on Linux kernel initiated MPIPL. As : - Linux initiated MPIPL calls platform termination function directly - ELF core format needs crashing CPU details to generate proper code Hence I think it makes sense to move this back to platform specific terminate handler code. Today we have two ways to trigger MPIPL based on service processor. - On BMC system we call SBE S0 interrupt - On FSP system we call `attn` instruction In future if we add new ways to trigger MPIPL then we have to add platform specific support code anyway. That way its fine to move this to platform sepcific code. One alternative is to make this call in all code path before making platform.terminate call... which makes it more complicated than above approach. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-30mpipl: Delay MPIPL registration until OPAL init is completeVasant Hegde4-4/+18
If OPAL boot fails after MPIPL init (opal_mpipl_init()) then we call MPIPL boot instead of reboot. BMC is not aware of MPIPL. Hence it may result in continuous MPIPL loop (boot -> crash -> MPIPL -> boot). If OPAL boot fails (before loading kernel) then its better to call reboot. So that BMC can detect `n` number of boot failures (generally n = 3) and stop booting. That way we can avoid continuous loop. This patch moves MPIPL init to the end of init process (just before starting kernel). So that if we fail to boot OPAL we call normal reboot. Also this patch introduces new function to detect MPIPL is enabled or not (is_mpipl_enabled()). And in assert() path we check for this function instead of `dump` DT node. So that it will make sure we will not call MPIPL until opal_mpipl_init is complete. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-30uart: Actually swallow data if LPC is not workingVasant Hegde1-1/+1
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-30dt: Set new property length in dt_resize_property()Thiago Jung Bauermann6-5/+1
All callers of dt_resize_property() need to set the new property length after calling it. append_chip_id() wasn't doing it, which caused this assert when booting my machine: [ 136.387213258,3] Unable to use memory range 0 from MSAREA 0 [ 136.387356677,3] Unable to use memory range 0 from MSAREA 2 [ 136.387408390,3] *********************************************** [ 136.387454272,3] < assert failed at core/device.c:605 > [ 136.387493225,3] . [ 136.387512799,3] . [ 136.387534056,3] . [ 136.387550294,3] OO__) [ 136.387579530,3] <"__/ [ 136.387605086,3] ^ ^ [ 136.387719329,3] Fatal TRAP at 0000000030028a18 .dt_property_set_cell+0x34 MSR 9000000000021002 [ 136.387801707,3] CFAR : 00000000300bfd3c MSR : 9000000000001000 [ 136.387847032,3] SRR0 : 0000000030028a18 SRR1 : 9000000000021002 [ 136.387893119,3] HSRR0: 0000000030012524 HSRR1: 9000000000001000 [ 136.387936830,3] DSISR: 40000000 DAR : 00000002019df000 [ 136.387983570,3] LR : 00000000300bfd40 CTR : 0000000000000000 [ 136.388046031,3] CR : 20004202 XER : 00000000 [ 136.388094553,3] GPR00: 00000000300bfd40 GPR16: 0000000000000001 [ 136.388139862,3] GPR01: 0000000031e536e0 GPR17: 00000000300ca3c9 [ 136.388181131,3] GPR02: 0000000030121200 GPR18: 0000000030103e1c [ 136.388224105,3] GPR03: 000000003053fc60 GPR19: 0000000000000008 [ 136.388270356,3] GPR04: 0000000000000001 GPR20: 000000003053fba0 [ 136.388313950,3] GPR05: 0000000000000008 GPR21: 0000000000000001 [ 136.388363021,3] GPR06: 0000000031e50060 GPR22: 0000000000000001 [ 136.388416754,3] GPR07: 0000000000000000 GPR23: 0000000000000000 [ 136.388465729,3] GPR08: 0000000000000000 GPR24: 0000000000000000 [ 136.388508156,3] GPR09: 0000000000000004 GPR25: 0000000031204060 [ 136.388556203,3] GPR10: 0000000000000008 GPR26: 000000003120402c [ 136.388599076,3] GPR11: 0000000000000000 GPR27: 0000000030010000 [ 136.388642108,3] GPR12: 0000000040004204 GPR28: 0000000000000002 [ 136.388694064,3] GPR13: 0000000031e50000 GPR29: 0000000031203ee0 [ 136.388743298,3] GPR14: 00000000300cbf03 GPR30: 0000000031202e80 [ 136.388797131,3] GPR15: 00000000300cc01c GPR31: 0000000030103a33 CPU 0048 Backtrace: S: 0000000031e539e0 R: 0000000030028874 .dt_resize_property+0x28 S: 0000000031e53a60 R: 00000000300bfd40 .memory_parse+0xd84 S: 0000000031e53c40 R: 00000000300bc4d8 .parse_hdat+0xed0 S: 0000000031e53e30 R: 000000003001504c .main_cpu_entry+0x1ac S: 0000000031e53f00 R: 0000000030002760 boot_entry+0x1b0 Avoid further appearances of the unidentified animal of doom by making dt_resize_property() do the length updating itself, freeing its callers from that need. Suggested-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Thiago Jung Bauermann <bauerman@linux.ibm.com> Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-30xive/P9: Use NUM_INT_PRIORITIES in xive_reset()Cédric Le Goater1-1/+1
Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-30xive/p9: Introduce XIVE_ESB_SIZECédric Le Goater1-7/+8
Replace 0x20000 with a clear define. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-30xive/p9: use PAGE_SIZECédric Le Goater1-19/+19
Signed-off-by: Cédric Le Goater <clg@kaod.org> [oliver: added prev patch, minor style fix] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-30hw/xive: Use XIVE_VSD_SIZE moreOliver O'Halloran1-2/+2
I think Cedric forgot this patch at some point. Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-30xive/p9: Introduce definitions for VP ids of HW threadsCédric Le Goater1-13/+22
The CAM line of the HW context is 23bits wide and its value is hardcoded in the XIVE IC presenter with : |chip|000000000001|thrdid | To make sure that we won't assign a VP id overlapping with the HW CAM line, we reserve range 0x80..0xff in our VP allocator. Make that clear. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-30xive/p9: Modify the size of the VP spaceCédric Le Goater1-8/+12
The VP space is 19bits wide but the number of XIVE VPs software can use depends on the configured number of EQs. We have 1M EQs and we use 8 priorities per VP. Therefore, our VP space is limited to 128k. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-30xive/p9: Force 64K page size on the IC and TM BARsCédric Le Goater1-21/+6
It is possible to configure the IC and TM BAR mappings using 4k pages but we never do. Remove the code doing so. Reviewed-by: Gustavo Romero <gromero@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-30xive/p9: Clarify indirect table allocationCédric Le Goater1-12/+17
The XIVE interrupt controller uses a set of Virtualization Structure Tables (VST) which characteristics, type, address, size, are described by Virtual Structure Descriptors (VSD). A VSD is 64bit wide. The EQ and VP tables are indirect tables. The VSD points to a single page of VSDs each pointing to a page of virtual structures. Indirect tables are limited to a single top page which is enough to cover the whole range of EQs (24 bits) and VPs (19bits). Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-30xive/p9: Use sizeof() instead of hardcoded valuesCédric Le Goater1-2/+3
Reviewed-by: Gustavo Romero <gromero@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-30xive/p9: Introduce XIVE_EQ_SHIFTCédric Le Goater1-2/+3
Each EQ descriptor is associated with a pair of ESB pages. The even page controls the ESn PQ bits and the odd page controls the ESe PQ bits. Reviewed-by: Gustavo Romero <gromero@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-30xive/p9: Clarify the escalation IRQ encodingCédric Le Goater1-4/+9
When an interrupt can not be delivered, an escalation interrupt can be triggered. The EQ descriptor of the pending interrupt should be configured to generate an escalation event, using the EQ_W0_ESCALATE_CTL 'e' bit, and words 4 and 5 of the EQ descriptor should contain an IVE pointing to the escalation EQ to trigger. This is why EQ descriptors are considered as interrupt sources and registered as such when initializing the interrupt controller. These interrupts are identified as escalations by the OPAL XIVE interface, OPAL calls and internal routines, by setting a special bit in their global interrupt number. Clarify that and check that the number of EQ descriptors is not overflowing the global interrupt encoding. Reviewed-by: Gustavo Romero <gromero@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-30xive/p9: Introduce XIVE_EQ_ORDERCédric Le Goater1-8/+9
XIVE_EQ_ORDER defines the number of EQ descriptors per chip the system can use. The EQ descriptors can be controlled by ESB pages also and the driver defines in the VC BAR of the controller a range of 128G of ESB pages giving access to 1M EQs. All ESB pages are backed by a memory table, so we are fine but we could improve the configuration. Reviewed-by: Gustavo Romero <gromero@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-30xive/p9: Introduce XIVE_ESB_SHIFTCédric Le Goater1-4/+6
Each interrupt source is associated with a pair of ESB pages. The even page is for trigger and the odd page is for management. Reviewed-by: Gustavo Romero <gromero@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-30xive/p9: Clarify the global IRQ number encodingCédric Le Goater1-6/+13
On P9, the global IRQ number is limited to 24 bits because the XICS emulation encodes the CPPR value in the top 8 bits. The following 4 bits are used to encode the XIVE block number, which leaves 20 bits for the interrupt index number. Introduce a definition reflecting the size of this bitfield and check that number of interrupts per chip is not overflowing our encoding. Reviewed-by: Gustavo Romero <gromero@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-30xive/p9: Introduce XIVE_INT_ORDERCédric Le Goater1-14/+20
The size of the interrupt number space is constrained by the block and index fields of the trigger data exchanged between source units and the XIVE IC. These are respectively 4 and 28 bits, which gives us a 32 bits interrupt number space. But the XICS emulation requires 8 bits to encode the CPPR value. The system interrupt number space is therefore constrained to 24 bits and on a chip, to 20 bits because the XIVE driver configures the HW to use one block per chip. XIVE_INT_ORDER defines the size of the interrupt number space : 1M per chip. To control these interrupts, the driver defines in the VC BAR of the controller a range of 384G of ESB pages giving access to 3M interrupts. The VSD for the memory table is smaller than the index and accesses to some ESB pages are not backed by a memory table structure. If such an access occurred, it would result in a FIR. It never happened but this is something to fix with a finer configuration of the VC BAR. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-17platform/mihawk: Fix IPMI double-freenichole1-2/+0
The commit 6826095 ("platform/mihawk: support dynamic PCIe slot table") added the IPMI OEM command to communicate with BMC. We do the ipmi_free_msg(msg) twice that caused the Fast-reboot fail. This patch fixes it by removing the IPMI double-free bug to restore Fast-reboot. Signed-off-by: Nichole Wang <Nichole_Wang@wistron.com> Cc: skiboot-stable@lists.ozlabs.org # skiboot-6.6.x Cc: skiboot-stable@lists.ozlabs.org # skiboot-op940.x Fixes: commit 6826095 ("platform/mihawk: support dynamic PCIe slot table") Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-17test: Print proper mambo command pathVasant Hegde1-1/+1
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-17travis: Add clang specific build jobOliver O'Halloran8-9/+23
Right now clang doesn't support the -ffixed-r<number> compiler options that we rely on for the skiboot cpu_thread pointer so it can't build skiboot. Remove the clang builds from the debian-unstable and ubuntu-latest and builds in favour of a clang specific job. This allows those jobs to pass normally and gives us as specific job to monitor to see when support for those options lands in clang. Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-17makefile: Supress Werror on clangOliver O'Halloran1-0/+5
We get a lot more warnings from clang so disable Werror for now so it fails to compile elsewhere. Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-17Makefile: Add -Werror to try-cflag so it works on clangOliver O'Halloran1-2/+2
Clangs prints warnings when it sees unknown command line options. Adding -Werror to the command line to upgrade them to errors results in clang exiting with exit code 1 which is what try-cflag expects. Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-17test: Do gcov builds as a seperate passOliver O'Halloran6-13/+9
We only really use the gcov output when doing the coverage report as a part of the "docs" CI builds. It's useful for development to just run the unit tests so make sure the "check" and "coverage" targets are seperate. This also speeds up our CI builds since those jobs are already doing a seperate GCOV pass so building and running the GCOV binaries during the check pass is redundant. Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-17test: Add an external-check targetOliver O'Halloran1-1/+3
To go along with core-check and friends. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-17travis: Disable seccomp on child containersOliver O'Halloran1-0/+1
We've been hitting the following issue with valgrind breaking when run inside a Fedora 32 container: [ BOOT TEST ] ccan/check_type/test/run valgrind: ccan/check_type/test/run: Operation not permitted make: *** [/build/ccan/Makefile.check:24: ccan/check_type/test/run-check] Error 126 make: *** Waiting for unfinished jobs.... This seems to be a result of the default seccomp profile blocking system calls that valgrind wants to use to inspect the process being debugged (i.e. ptrace). Fix this by using the unrestricted seccomp profile and giving the container the ptrace capability. Travis uses ephemereal VMs for each job so this isn't any kind of security issue. Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-17travis: Add an explicit tmpfs mountOliver O'Halloran1-0/+1
A tempfs mount is missing on fedora 32 which seems to be causing errors when testcases attempt to write there. Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-17travis: Allow ubuntu-latest to failOliver O'Halloran1-0/+1
Ubuntu-latest is a rolling development release, similar to rawhide. There's no need to treat failing there as an actual error. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-17travis: move container build into the install stepOliver O'Halloran1-2/+11
Travis automatically hides the output of completed build stages. Moving the `docker build` output into the install stage results in less spam to wade through while looking at CI failures. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-17ci: Remove lcov workaround for FedoraOliver O'Halloran1-4/+2
The bug being worked around here was fixed ages ago in F29 and F30. There's no need to continue using the testing version of lcov so go back to using the production version. Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-17ci: Fix docs buildOliver O'Halloran1-6/+0
The docs build uses the Fedora32 container environment, but we didn't update the script when we moved to Fedora 32. Do that. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-17ci: Drop debian strechOliver O'Halloran2-2/+0
This used the same build script as ubuntu 16.04 and is now broken. Remove it also. Signed-off-by: Oliver O'Halloran <oohall@gmail.com>t Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-17travis: Update configOliver O'Halloran1-20/+18
Move to using Ubuntu 18.04 rather than 14.04 (which has been out of support for years now) and fix up some warnings from the config file checker. Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-17travis: Remove the unused coverity tokenOliver O'Halloran1-4/+3
In 7cd8402c3bec the coverity job config was moved to a seperate branch. The encrypted token was left in the main .travis.yaml file though so travis includes the token in the web interfaces which crowds out the information we actually care about (which docker container we used). Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-17test/qemu: Update command line argumentsOliver O'Halloran2-2/+4
Modern qemu builds will barf if you specify the BMC / ipmi device on the command line without -nodefaults. So add that in and put in an explicit serial device. Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-11hdata: MS AREA endian fixNicholas Piggin1-3/+3
Signed-off-by: Nicholas Piggin <npiggin@gmail.com> [oliver: fix up drift] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-11include/ocmb.h: Add a newline to end of fileNicholas Piggin1-1/+1
Sparse complains about no newline at end of file. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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