| Age | Commit message (Collapse) | Author | Files | Lines |
|---|
|
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
|
|
Core IMC hardware mandates initiating of three scoms to enable or
disable of the Core IMC engine. This has to be done for each core,
and is done in the opal_imc_counters_init().
In fused core mode, the scom has to be done explicitly for the secondary
core to enable or disable core IMC engine in that core.
Do the scom for the secondary core, by calculating the core id from
the incoming cpu id.
This patch is based on the series,
Initial fused-core support for POWER9 [v5]:
https://lists.ozlabs.org/pipermail/skiboot/2020-April/016778.html
Signed-off-by: Anju T Sudhakar <anju@linux.vnet.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
|
|
The xscom macros defined in the skiboot are platform specific.
IMC opal APIs use these xscom definitions, to read and write to scom
ports. Cleanup the code to pick the appropriate xscom macro definition
based on the running platform.
Signed-off-by: Anju T Sudhakar <anju@linux.vnet.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
|
|
Currently scom addresses for IMC are defined at compile time.
The scom addresses may vary for different processor generations.
So clean up the code to pick the right scom addresses, based on
the processor version at run time.
Signed-off-by: Anju T Sudhakar <anju@linux.vnet.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
|
|
Starting from p10 hostboot will no longer clear all the system memory except
its own space. OPAL uses the memory at SKIBOOT_BASE + SKIBOOT_SIZE for cpu
stack with pir as index. With hostboot no longer clearing memory this region
may hold junk contents. Currently opal initialize cpu stack memory only for
cpu pir that is found on the device-tree. For the rest, the cpu thread
contents are uninitialized. This sometime causes for_each_cpu* macros to
return cpu thread for pir/cpu which isn't present on the system. The
for_each_cpu* macros iterate over cpu stacks using pir as index and returns
cpu thread pointer if state != cpu_state_no_cpu. For cpus that are not found
on device-tree the state may hold junk value leading OPAL to access invalid
cpu thread area. This further leads to accessing pointers with junk values
causing machine check (MCE) during OPAL init code. Fix this by Initializing
all the cpu thread areas upto cpu_max_pir.
[ 182.049714372,3] ***********************************************
[ 182.049878580,3] Fatal MCE at 0000000030039738 .init_trace_buffers+0x21c MSR 9000000000201002
[ 182.049943811,3] Cause: load real address error
[ 182.049968681,3] Effective address: 0x480113a4791c4a50
[ 182.050000736,3] CFAR : 00000000300395b8 MSR : 9000000000201002
[ 182.050035376,3] SRR0 : 0000000030039738 SRR1 : 9000000000201002
[ 182.050072878,3] HSRR0: 0000000030020024 HSRR1: 9000000000001000
[ 182.050117303,3] DSISR: 00000040 DAR : 480113a4791c4a50
[ 182.050149054,3] LR : 0000000030039744 CTR : 0000000000000000
[ 182.050182991,3] CR : 42000224 XER : 00000000
[ 182.050217262,3] GPR00: 000000003003962c GPR16: 0000000032d50000
[ 182.050255746,3] GPR01: 0000000032d53a50 GPR17: 0000000030003198
[ 182.050288081,3] GPR02: 000000003014cb00 GPR18: 0000000000000000
[ 182.050331474,3] GPR03: 0000000031c50000 GPR19: 0000000000000000
[ 182.050371934,3] GPR04: 0000000000000000 GPR20: 0000000000000000
[ 182.050416212,3] GPR05: ffffffffffffffff GPR21: 0000000000000001
[ 182.050454130,3] GPR06: 0000000000000005 GPR22: 00000000300f74eb
[ 182.050488053,3] GPR07: 0000000000000028 GPR23: 00000000000fffd8
[ 182.050522774,3] GPR08: 000000000000067f GPR24: 00000000000fff40
[ 182.050566878,3] GPR09: 480113a4791c4a18 GPR25: 0000000000000070
[ 182.050601524,3] GPR10: 00000000078b0353 GPR26: 00000000300f7527
[ 182.050640345,3] GPR11: 0000000000000000 GPR27: 00000000300f7516
[ 182.050680816,3] GPR12: 0000000042000222 GPR28: 000000003acd0000
[ 182.050724099,3] GPR13: 000000000025a908 GPR29: 000000003acd0000
[ 182.050759728,3] GPR14: 0000000000000000 GPR30: 0000000000000000
[ 182.050790430,3] GPR15: 0000000000000000 GPR31: 00000000301f0038
CPU 0228 Backtrace:
S: 0000000032d53d60 R: 000000003003962c .init_trace_buffers+0x110
S: 0000000032d53e30 R: 0000000030022f84 .main_cpu_entry+0x550
S: 0000000032d53f00 R: 00000000300031f8 not_fused+0x11c
Signed-off-by: Mahesh Salgaonkar <mahesh@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
[Folded Nick's patch to that added mark_all_secondary_cpus_absent() - Vasant]
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
|
|
Without this the shared SPRs on the secondary cores are not set.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
|
|
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Vaidyanathan Srinivasan <svaidy@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
|
|
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
|
|
Prepare for POWER10 support which changes the OCCFLG register base
address.
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
[Replaced perror with prlog - Vasant]
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
|
|
When booting skiboot we initialise any I2C masters after probing the
platform, but before initialising the platform (or NVRAM). Due to this we
need to ensure that all the I2C masters we might want to use are in the DT
before the platform is initialised. This causes problems since we might
want to add another master (e.g. on witherspoon we might need to add a port
for the I2C OpenCAPI I2C bus).
It's possible to hack around this by adding a new node in the probe
function, but the probe function runs very early before many essential
services are initialised (e.g. LPC). We might want to add another I2C bus
after learning that we have a riser card installed and it's not possible to
do that until later in boot.
To accommodate those use cases we can add support for adding a new bus at
runtime.
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
|
|
We've got functions to instantiate I2C buses at various places inside of
the skiboot code base (in hdat, firenze-pci, and in witherspoon). The
HDAT ones are the most generic so re-work those a bit and export the
functions used to add DT nodes for I2C masters and the ports below them.
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
|
|
Move it out in preparation for adding the ability to add new ports on
the fly.
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
|
|
The rate at which we need to poll the master depends on the speed of the
bus. Faster I2C buses will require more frequent polling so it doesn't
make a whole lot of sense to set this on a per-master basis. This patch
sets the master's polling interval to a per-port setting calculated
from the port speed.
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
|
|
Whether I2C interrupts work or not depends on the type of master.
Currently we print a single message to indicate whether IRQs work or
not, but this will be wrong if we have I2C interrupts on the host and
we happen to probe a Centaur I2C master first. Fix this by adding a
message to the per-master print indicating whether the master has
an interrupt or not.
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
|
|
Adds a way to find the struct i2c_bus for a given chip ID, engine ID,
and port ID. HDAT indicates which I2C master is relevant using this
information so it comes up a fair bit.
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
|
|
Add support for tracing I2C transactions performed by skiboot. This covers
both internally initiated I2C ops and those that requested by the kernel
via the OPAL API.
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
|
|
Previously we put all the trace buffer exports in the exports/ node.
However, there's one trace buffer for each core so I moved them into a
subdirectory since they were crowding up the place. Most kernels don't
support recursively exporting subnodes though so kernel's don't have
support for recursively exporting subnodes, so add a hack to restore the
old behaviour for now.
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
[Fixed run-trace test case - Vasant]
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
|
|
Make the trace tool's output format match that of skiboot's prlog().
Printing a timebase tick count in hex isn't terribly useful and having
a common format makes correlating trace entries to log entries much
easier.
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
|
|
Not all kernels support mmap() on an OPAL exported memory range. Fall
back to allocating a buffer and using the normal file IO system calls
to read the contents of the trace buffer in those cases.
This does mean we can't use "follow" mode since we can't monitor the
raw trace data effectively, but otherwise it works fine.
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
|
|
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
|
|
Setting the Remote Memory Access BAR address is used in a couple of
places which should be defined as a common function. On p10, paste
base address format is changed (using primary topology index instead
of node/chip IDs).
This patch adds p9_get_rma_bar() for P9. Whereas get_rma_bar() on P10
and future processors which will be added in later patches.
Signed-off-by: Haren Myneni <haren@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
|
|
Async machine check errors due to bad real address from store or
foreign link time out comes with the load/store bit (PPC bit 42)
set in SRR1 but the cause is set in SRR1 not DSISR, unlike other
errors that have the load/store bit set.
This behaviour was omitted from the POWER9 User Manual but it is
confirmed to be the expected one. Update the machine check decoder
to match.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
|
|
cpu_pm_idle sets pm_enabled = false and expected all cpus
to exit idle. This is needed to re-enter with new settings.
Right after cpu_bringup() we call copy_sreset_vector() and then
cpu_set_sreset_enable(true). At this time some cpus are still
yet to enter idle and hence miss the doorbell to wakeup.
This leads to cpu_pm_idle waiting forever. This pattern happens
on some system in fused-core mode.
The fact that pm_enabled flag is changing right in the middle of
idle entry is see from the "cpu_idle_p9 called with pm disabled" traces.
One method to fix this race is to retry the door-bell after a timeout.
This patch implements a small time out (few seconds) and then issues
the doorbell once again to kick the cpu that entered idle late after
missing the pm_enabled = false flag.
This checking loop run in smt_lowest() and hence the timeout number
maps to couple of seconds which is sufficient to let the cpus settle in
idle and make them see the doorbell and exit.
Example boot log:
[ 288.309322810,7] INIT: CPU PIR 0x000d called in
[ 288.309320768,7] INIT: CPU PIR 0x000b called in
[ 288.314603802,7] INIT: CPU PIR 0x0020 called in
[ 288.321303468,5] CPU: All 88 processors called in...
[ 288.315056796,6] cpu_idle_p9 called on cpu 0x024e with pm disabled
[ 288.321308091,6] cpu_idle_p9 called on cpu 0x0264 with pm disabled
[ 288.314424259,6] cpu_idle_p9 called on cpu 0x025b with pm disabled
[ 288.324928307,6] cpu_idle_p9 called on cpu 0x0065 with pm disabled
[ 305.207316004,6] cpu_pm_disable TIMEOUT on cpu 0x0261 to exit idle
[ 322.093298501,6] cpu_pm_disable TIMEOUT on cpu 0x0263 to exit idle
[ 338.491281028,6] cpu_pm_disable TIMEOUT on cpu 0x0265 to exit idle
[ 355.377263492,6] cpu_pm_disable TIMEOUT on cpu 0x0267 to exit idle
[ 372.263245960,6] cpu_pm_disable TIMEOUT on cpu 0x0269 to exit idle
[ 389.149228389,6] cpu_pm_disable TIMEOUT on cpu 0x026b to exit idle
[ 406.035210852,6] cpu_pm_disable TIMEOUT on cpu 0x026d to exit idle
[ 422.433193381,6] cpu_pm_disable TIMEOUT on cpu 0x026f to exit idle
[ 422.433277720,6] CHIPTOD: Calculated MCBS is 0x25 (Cfreq=2000000000 Tfreq=32000000)
Reported-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Signed-off-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com>
[Reworded commit message - Vasant]
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
|
|
We only handle sha256 hashes in auth structures.
In the process of verifying an auth structure, we extract the pkcs7
message and we calculate the hopefully-matching hash, which is
sha256(name || vendor guid || attributes || timestamp || newcontent)
We then verify that the PKCS#7 signature matches that calculated hash.
However, at no point do we check that the PKCS#7 hash algorithm is
sha256. So if the PKCS#7 message says that it is a signature on a sha512,
mbedtls will compare 64 bytes of hash from the signature with 64 bytes
from our hash, resulting in a 32 byte overread.
Verify that the hash algorithm in the PKCS#7 message is sha256.
Add a test.
Signed-off-by: Daniel Axtens <dja@axtens.net>
Reviewed-by: Nayna Jain <nayna@linux.ibm.com>
Tested-by: Nayna Jain <nayna@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
|
|
unpack_timestamp() calls le32_to_cpu() for endian conversion of
uint16_t "year" value. This patch fixes the code to use le16_to_cpu().
Signed-off-by: Nayna Jain <nayna@linux.ibm.com>
Reviewed-by: Daniel Axtens <dja@axtens.net>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
|
|
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
|
|
Increase timeout introduced in commit 6bf21350da32 ("uart: Drop
console write data if BMC becomes unresponsive") when running under
SIMICS.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
|
|
Move to qemu version powernv-6.0. Also add required packages.
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
|
|
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
|
|
This isn't currently used in skiboot but may be used by external
users of skiboot's secvar code.
Signed-off-by: Daniel Axtens <dja@axtens.net>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
|
|
We use these types but haven't included the header: every file that
includes edk2.h has already included it.
This might not be true for other users of edk2.h and skiboot's secvar
code, so include it explictly.
Signed-off-by: Daniel Axtens <dja@axtens.net>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
|
|
If allocating the secure variable name of a secure variable struct,
`secvar->key`, fails then the secvar struct should be freed before
returning NULL. Previously, if this allocation fails, then only the
`secvar->key` is freed (which is likely a typo) leaving the allocated
`secvar` struct allocated and returning NULL. This memory leak can be
seen with the static analysis tool `cppcheck`. After running valgrind
tests, this commit ensures that memory is properly freed if an error
occurs when allocating the `key` field of the `secvar` struct.
Signed-off-by: Nick Child <nick.child@ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
|
|
Functions `get_esl_cert`, `validate_esl_list` and
`get_esl_signature_list_size` all contain the same debug print
statement. This statement prints the size of the ESL.
`validate_esl_list` calls `get_esl_cert` so the same debug information
prints twice when validating the newly submitted ESL. Additionally,
the same debug prints twice when validating the current ESL since
`get_esl_cert` and `get_esl_signature_list_size` are both called by
the function `verify_signature`. Since `get_esl_cert` is the common
factor, this commit removes the other two print statements (and adds
some information to an error message to maintain clarity, in case
`validate_esl_list` fails before calling `validate_esl_cert`). After
double checking that these functions are not being called anywhere
else, the only real change is to reduce the number of redundant print
statements for the secvar update process.
Signed-off-by: Nick Child <nick.child@ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
|
|
During opal boot, in imc_init(), 24x7/IMC microcode state is checked
and if it is not in running or pause state, currently all the
imc devices are removed from device tree. Instead, remove only
the nest imc devices. Core/Thread/Trace imc devices are not related
to 24x7 microcode. Patch adds a function to remove specific imc
device type and the same is used, when pause_microcode() fails, to
remove nest imc device types from the device tree.
Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
|
|
imc_init() checks for the 24x7 microcode state at boot to
check whether the microcode is in proper state (running or paused).
But in a larger system, loading of 24x7 microcode by OCC gets delayed.
Because of this, imc_init() removes imc devices from the device tree.
Moving imc_init() function towards end of the main_cpu_entry()
works around this.
Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
|
|
Hitting below issue on recent distro (fedora-rawhide).
sample failure:
---------------
[ HOSTCC ] hw/ipmi/test/run-fru.c
In file included from hw/ipmi/test/run-fru.c:10:
hw/ipmi/test/../ipmi-fru.c: In function 'fru_fill_product_info':
hw/ipmi/test/../ipmi-fru.c:80:17: error: this 'if' clause does not guard... [-Werror=misleading-indentation]
80 | if (rc < 1) return OPAL_PARAMETER; rc; })
| ^~
hw/ipmi/test/../ipmi-fru.c:102:18: note: in expansion of macro 'FRU_INSERT_STRING'
102 | index += FRU_INSERT_STRING(&buf[index], info->manufacturer);
| ^~~~~~~~~~~~~~~~~
hw/ipmi/test/../ipmi-fru.c:80:52: note: ...this statement, but the latter is misleadingly indented as if it were guarded by the 'if'
80 | if (rc < 1) return OPAL_PARAMETER; rc; })
| ^~
hw/ipmi/test/../ipmi-fru.c:102:18: note: in expansion of macro 'FRU_INSERT_STRING'
102 | index += FRU_INSERT_STRING(&buf[index], info->manufacturer);
| ^~~~~~~~~~~~~~~~~
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Reviewed-by: Dan Horák <dan@danny.cz>
|
|
openssl is needed by libstb.
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Reviewed-by: Dan Horák <dan@danny.cz>
|
|
Ideally we should move to fedora34. But looks like docker repository
doesn't have fedora34-ppc64le image. Hence moving to fedora33 for now.
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Reviewed-by: Dan Horák <dan@danny.cz>
|
|
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Reviewed-by: Dan Horák <dan@danny.cz>
|
|
Convert scripts to Python3 as Python2 has been EOLed in 2020.
Fixes: https://github.com/open-power/skiboot/issues/225
Signed-off-by: Dan Horák <dan@danny.cz>
[Fixed directory walking logic in generate-fwts-olog - Vasant]
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
|
|
The structes we import from EDK2 are expected to be packed.
The code we imported does this a #pragma pack, but it doesn't
restore the original non-packed state at the end of the header.
Rather than changing that, just explictly pack every structure.
The resulting skiboot.elf has the same disassembly (objdump -dr)
and readelf -a output, but I haven't been able to test this on
a real machine.
Signed-off-by: Daniel Axtens <dja@axtens.net>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
|
|
The commit f397cc30bdf8 ("phb4: Only escalate freezes on MMIO load where
necessary") introduced a change to restrict escalation to the chips that
actually need it. However it missed one case which still causes the
escalation on every chip. This affects EEH recovery to cause full
PHB reset on some chips which is not necessary. This patch fixes that.
Also, add a check for p9 chip in phb4_escalation_required() function.
Cc: skiboot-stable@lists.ozlabs.org
Signed-off-by: Mahesh Salgaonkar <mahesh@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
|
|
The commit e73cf72d1f97 ("phb4: make endian-clean") accidently missed
printing correct value for PCI device secondary status register.
[ 1654.399387394,3] PHB#0033[3:3]: devCmdStatus = 00100107
[ 1654.399389575,3] PHB#0033[3:3]: devSecStatus = 00100107
after this patch:
[ 1620.415289504,3] PHB#0033[3:3]: devCmdStatus = 00100107
[ 1620.415291622,3] PHB#0033[3:3]: devSecStatus = 00002000
Fixes: e73cf72d ("phb4: make endian-clean")
Signed-off-by: Mahesh Salgaonkar <mahesh@linux.ibm.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
|
|
This patch implements a circumvention for HW557787. It disables the
TCE cache line buffer as, under heavy loads, there's a possibility of
an entry being re-allocated incorrectly.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
|
|
Follow the inclusive terminology from the "Conscious Language in
your Open Source Projects" guidelines [*] and replace the word
"whitelist" appropriately.
[*] https://github.com/conscious-lang/conscious-lang-docs/blob/main/faq.md
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
|
|
Follow the inclusive terminology from the "Conscious Language in
your Open Source Projects" guidelines [*] and replace the word
"whitelist" appropriately.
[*] https://github.com/conscious-lang/conscious-lang-docs/blob/main/faq.md
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
|
|
Follow the inclusive terminology from the "Conscious Language in
your Open Source Projects" guidelines [*] and replace the word
"whitelist" appropriately.
[*] https://github.com/conscious-lang/conscious-lang-docs/blob/main/faq.md
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
|
|
BT IRQ may preempt BT timer if BMC response host when bt msg timeout.
When BT IRQ preempt BT timer, the infight_bt_msg did not protected by bt.lock very well.
And we will see the following log:
[29006114.163785853,3] BT: seq 0x81 netfn 0x0a cmd 0x23: Timeout sending message
[29006114.288029290,3] BT: seq 0x81 netfn 0x0b cmd 0x23: Timeout sending message
[29006114.288917798,3] IPMI: Incorrect netfn 0x0b in response
It may cause 'CPU Hardlock UP', 'memory refree', 'kernel crash' or something else...
Signed-off-by: lixg <867314078@qq.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
|
|
This just keeps the requested delta and uses it to adjust subsequent
rtc_read calls.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
|
|
Currently we are not accounting cancelled timer request. So in some
corner cases we may schedule new timer request with
new-timer-value > inflight-timer-value.
Lets explicit check new_target value with inflight timer value.
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
|
