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2021-10-19phb4: annotate tbl_pest with endian typesNicholas Piggin2-13/+8
Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19asm/head: Fix P10 HILE for little endian buildNicholas Piggin1-0/+5
Fixes: 891ed8df67 ("Initial POWER10 enablement") Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19cpu: add debug check in cpu_relaxNicholas Piggin2-0/+7
If cpu_relax() is called when not at medium SMT priority, it will lose the prior priority and return at medium. Add a debug check to catch this, which would have flagged the previous bug. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19cpu: cpu_idle_job SMT priority fixNicholas Piggin1-1/+0
Calling cpu_relax resets the SMT priority to medium, causing the idle loop not to run with lowest priority. Just use barrier() instead, this saves about 3 seconds on a SMT4 systemsim (mambo) boot. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19interrupts: add_opal_interrupts avoid NULL dereference on P10 mamboNicholas Piggin2-1/+9
On P10, get_ics_phandle() calls xive2_get_phandle() directly. This results in a NULL dereference on mambo when xive2 is not set up. This was caught with the virtual memory boot patch on P10 mambo. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-13HBRT: fix clobbered r16 when host services handlers are calledNicholas Piggin3-6/+134
Skiboot is using r16 as a fixed register containing this CPU pointer, but we can be called back into from hostboot via the host services interface, where r16 may have been set by hostboot. Switch this back to skiboot's CPU pointer before running host services handlers, and then restore it to the hostboot value before returning. Fixes: 11ce9612b3aa ("move the __this_cpu register to r16, reserve r13-r15") Reported-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Tested-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-02phb5: Remove obsolete capp-related propertiesFrederic Barrat1-7/+10
This patch removes the following properties from PHB entries in the device tree on P10, since there's no CAPP any more and the properties no longer make sense: ibm,phb-indications ibm,capp-timebase-sync ibm,capi-flags It has no effect on linux: some were already ignored and others won't even be read since the cxl driver (the only consumer) already fails early on P10. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-02external/mambo: Add POWER10 small-core modeNicholas Piggin1-4/+21
If the SMT configuration is not 8, set small-core mode in SIM_CTRL1 and PVR registers. Also allow only 1, 2, 4, or 8 threads, and only allow 1 and 2 threads if there is only one processor configured. This helps avoid strange crashes due to thread/core enumeration problems with unexpected threads per core. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-02external/mambo: Updates POWER9 SIM_CTRL1 to remove hardware atomic RCNicholas Piggin1-1/+4
Update SIM_CTRL1 bits to set ARC0/1, which disables atomic RC updates in hardware which matches implementation. Comment some remaining quirks with the P9 configuration. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-02external/mambo: Updates for POWER10 configuration for DD2.0Nicholas Piggin2-4/+16
Update PVR and mambo f000f bits: - Set POWER10 to DD2.0 Update SIM_CTRL and SIM_CTRL1 bits: - Set the LPAR-per-core mode bit. This is required for SMT KVM to work. - Set ARC0/ARC1 bits which enable atomic RC update interrupts (not hardware updates), which matches implementation. - Enable DEXCR, HAIL, ROP, BHRB disable, block BHRB writes in PR=0, and RFC02628 on POWER10. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-09-09secvar: Free md context on hash errorNick Child1-2/+2
There were a few instances in `get_hash_to_verify` where NULL is returned before unallocating the md context. This commit ensures that this memory is properly freed before returning. Signed-off-by: Nick Child <nick.child@ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-09-09npu3: Remove GPU support on SwiftFrederic Barrat12-3724/+4
npu3 was only used on the Swift platform to add support for GPUs (nvlink). The Swift platform has never left the lab and support for GPUs on it is pretty much dead. So let's remove it. The patch removes all related code. Device tree entries are no longer created and in the very unlikely case that someone is still trying to boot it, the linux nvlink discovery code should be quiet. Tested by booting on Swift with no GPU. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Reza Arbab <arbab@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-09-09docs: Add Swift, Mowgli & RainierMichael Ellerman1-0/+9
Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-09-09doc: Make it clear all existing platforms use Power9NMichael Ellerman1-9/+9
Update the table of platforms to make it clear which Power9 CPU each uses, currently they all use Power9N. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-09-09external/mambo: Print more info when the kernel is too bigMichael Ellerman1-2/+4
Make it a bit easier to boot large kernels by printing more info when the kernel is too big, so the user has some idea how much they need to adjust PAYLOAD_ADDR by. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-27hello_world: Add p10 mambo testsVasant Hegde2-0/+80
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-27ci: Bump qemu versionVasant Hegde1-1/+1
Move to qemu version powernv-6.1. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-27phb4/5: Escalate page-level TCE killsFrederic Barrat1-0/+8
An hw issue was found on P10 (HW560152) where a page-level TCE kill can be dropped if there are enough TCE kill requests already being processed. The net effect is that data integrity is not guaranteed. The circumvention is to stay away from page-level kills and escalate those to PE kills. Which hurts performance. It also affects P9. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-18interrupts: Do not advertise XICS support on P10Cédric Le Goater3-1/+17
We only support the XIVE interface. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-18xive/p10: Fix mismatch errors when DEBUG=1Cédric Le Goater2-0/+6
HW has some reserved fields which break the comparison when checking END cache updates. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-18xive/p10: Fix xive_special_cache_check when DEBUG=1Cédric Le Goater1-1/+1
The special cache check done when skiboot is compiled with DEBUG is incompatible with Automatic Context Save and Restore. Random data is written in the NVP to check that cache updates are correct but this can lead to a checkstop raised by the XIVE interrupt controller. When the NVP Valid (0) bit, the hardware controlled H (7) bit, and the Checked Out bit (45) are all ones at the same time, the HW thinks that the NVP entry is checked out by a thread and does not allow the cache write to occur. Make sure that the valid bit is not set on the NVP. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06hw/chiptod: Abort if core frequency is not setVasant Hegde1-0/+6
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06hw/chiptod: Retry the sync procedure on failureRyan Grimm1-10/+23
The chiptod sync will sometimes fail and then sync successfully after a retry. So, try an arbitrary 10 numbers of times before we either abort() on main procedure fail or disable threads on secondary procedure fail. Also, put a message on the log if secondaries fail so we have evidence in the log when they aren't enabled. Signed-off-by: Ryan Grimm <grimm@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06xive2: Add NCU_SPEC_BAR to stop engine for restoreVaidyanathan Srinivasan1-3/+24
P10 Stop engines have apis similar to P9 to set xscom restores after wakeup from deep-sleep states. This xscom restore will be used to support STOP11 on P10. Signed-off-by: Vaidyanathan Srinivasan <svaidy@linux.ibm.com> Signed-off-by: Pratik Rajesh Sampat <psampat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06libpore: P10 stop-api supportPratik Rajesh Sampat15-9/+4311
Update libpore with P10 STOP API. Add minor changes to make P9 stop-api and P10 stop-api to co-exist in OPAL. These calls are required for STOP11 support on P10. STIOP0,2,3 on P10 does not lose full core state or scoms. stop-api based restore of SPRs or xscoms required only for STOP11 on P10. STOP11 on P10 will be a limited lab test/stress feature and not a product feature. (Same case as P9) Co-authored-by: Pratik Rajesh Sampat <psampat@linux.ibm.com> Signed-off-by: Pratik Rajesh Sampat <psampat@linux.ibm.com> Co-authored-by: Vaidyanathan Srinivasan <svaidy@linux.ibm.com> Signed-off-by: Vaidyanathan Srinivasan <svaidy@linux.ibm.com> Co-authored-by: Ryan Grimm <grimm@linux.ibm.com> Signed-off-by: Ryan Grimm <grimm@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06phb5: Fix PHB max link speed definition on P10Frederic Barrat1-2/+2
Not all PHBs are capable of GEN5 speed on P10. In all PEC configurations, the first PHB is the only one which can handle GEN5. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06phb4/5: Fix PHB link width detection to avoid useless retrainingsFrederic Barrat2-11/+81
On P9 and P10, the PCI express controller (PEC) controls a set of 16 lanes, which can be grouped to form link(s) of various width (4, 8 or 16 lanes). A PCI host bridge (PHB) is handling each link. How many PHBs are active in each PEC is configurable per chip and vary between 2 chips in a system. Therefore PHBs have different link width. The link width of the PHB is used to check if the link is trained optimally and can cause link training retries if that's not the case. We were reading the max link width of a PHB from the link capability register of the PCI express capability of the root bridge. But that value is always an overshoot as it needs to accommodate any PEC configuration. It was hard to fault on P9, as a PEC needs to be trifurcated to start noticing a difference and the device-supported width can also mask it. But on P10, it's also noticeable on bifurcated configuration so it's a bit easier to spot. For example, on P10, PHB0 reports a supported width of 16 in its link capability register because that's what is needed in case of no furcation, but if the PEC is bifurcated or trifurcated, only 8 lanes are wired. So we won't be able to train at more than x8. If we believe the PHB is x16-capable, then we'll retrain the link, potentially several times, thinking it's not optimal, which is a waste of time. This patch finds out the real maximum link width of each PHB, which may require to go check the PEC configuration. The logic is the same on P9 and P10 though the hardware implementations differ slightly. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06phb4: Cleanup PEC config discovery in CAPI modeFrederic Barrat2-11/+16
Small cleanup when reading the PEC config when setting up CAPI, in preparation for P10. Scom addresses vary between P9 and P10 and we'll be accessing more than one PCI chiplet. No functional change. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06phb5: Workaround for PCI bug HW551382Frederic Barrat2-1/+36
The workaround forces a state machine deep in the PHB to start from scratch and to block its evolution until after the link has been reset. It applies on all paths where the link can go down unexpectedly, though it's probably useless on the creset path, since we're going to deep-reset the PHB anyway. But it doesn't hurt and it keeps the set/unset path symmetrical. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06phb5: Enable Gen5Michael Neuling1-4/+8
Registers for Gen5 have been initialized in a previous patch. So let's activate it! Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06phb5: Add register inits specific to Gen5Frederic Barrat2-7/+17
Update init sequence to take into account Gen5. Define default equlization settings if HDAT is not used. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06phb5: Activate StoreEOI for LSIsCédric Le Goater1-1/+1
Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06hw/phb5: Update PHB numbering to allow for virtual PHBsFrederic Barrat1-1/+1
Make room for a per-chip numbering of virtual PHBs used by opencapi. We can have up to 12 opencapi PHBs (two per PAU) on P10. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06xive/p10: Change alignment of the queue overflow pagesCédric Le Goater1-2/+18
The Memory Coherence Directory uses 16M "granule" to track shared copies of a cache line. If any cache line within the 16M range gets touched by someone outside of the group, the MCD forces accesses to any cache line within the range to include everyone that might have a shared copy. Allocate the queue overflow pages and use a 16M alignment to avoid sharing with other structures and reduce traffic on the PowerBus. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06xive/p10: Tune max_entries_in_modified when split_mode is onCédric Le Goater2-0/+2
This reduces the number of entries currently modified in the ESB cache. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06xive/p10: Activate has_array when PQ_disable is availableCédric Le Goater2-3/+10
hash_array is an Internal cache hashing optimization. It tracks for ESBs where the original trigger came from so that we avoid getting the EAS into the cache twice. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06xive/p10: Activate split mode for PHB ESBs when PQ_disable is availableCédric Le Goater2-0/+30
1/3rd of the cache is reserved for PHB ESBs and the rest to IPIs. This is sufficient to keep all the PHB ESBs in cache and avoid ESB cache misses during IO interrupt processing. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06xive/p10: Introduce a new OPAL_XIVE_IRQ_STORE_EOI2 flagCédric Le Goater2-1/+2
StoreEOI (the capability to EOI with a store) requires load-after-store ordering in some cases to be reliable. P10 introduced a new offset for load operations to enforce correct ordering and the XIVE driver has the required support since kernel 5.8, commit b1f9be9392f0. OPAL on P10 will advertise support of StoreEOI with a new flag. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06xive/p10: Add automatic Context Save and Restore supportCédric Le Goater3-1/+56
The save-restore feature is forced when available. It would have been better to introduce some negotiation but the CAM line value is returned by get_vp_info() before the save-restore feature can be enabled by KVM in xive_native_enable_vp(). This is compatible with the current KVM implementation for P9. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06xive/p10: Configure XIVE for fused coresCédric Le Goater2-1/+28
Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06hw/psi-p10: Configure interrupt offset before notify addrOliver O'Halloran1-10/+10
When configuring the XIVE notification address any currently pending interrupts will be delivered once the the valid bit in the BAR is set. Currently we enable the notify BAR before we've configured the global interrupt number offset for the PSI interrupts. If any PSI interrupt is we'll send an interrupt trigger notification to the XIVE with the wrong interrupt vector (0..15). This can potentially cause a checkstop since there may not be an EAS / IVT configure for that vector. Fix this by registering and masking all the PSI interrupts after we've configured the ESB BAR, but before configuring the notification address and offset. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06xive/p10: Introduce new capability bitsCédric Le Goater4-10/+61
These bits control the availability of interrupt features : StoreEOI, PHB PQ_disable, PHB Address-Based Trigger and the overall XIVE exploitation mode. These bits can be set at early boot time of the system to activate/deactivate a feature for testing purposes. The default value should be '1'. The 'XIVE exploitation mode' bit is a software bit that skiboot could use to disable the XIVE OS interface and propose a P8 style XICS interface instead. There are no plans for that for the moment. The 'PHB PQ_disable', 'PHB Address-Based Trigger' bits are only used by the PHB5 driver and we deduce their availability from the capabilities of the first XIVE chip. If called from a PHB4 driver, the capabilities should be set to false. Signed-off-by: Cédric Le Goater <clg@kaod.org> [FB: port to phb4.c] Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06psi/p10: Mask all sources at initCédric Le Goater1-0/+7
Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06psi/p10: Introduce xive2_source_mask()Cédric Le Goater3-1/+19
Commit fa161cd89fbf ("hw/psi-p9: Mask OPAL-owned LSIs without handlers") introduced xive_source_mask(). Do the same for P10. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06hw/phb5: Add support for 'Address-Based Interrupt Trigger' modeCédric Le Goater3-12/+59
The PHB5 introduces a new Address-Based Interrupt mode which extends the notification offloading to the ESB pages. When ABT is activated, the PHB maps the interrupt source number into the interrupt command address. The PHB triggers the interrupt using directly the IC ESB page of the interrupt number and does not use the notify page of the IC anymore. The PHB interrrupt configuration under ABT is a little different. The 'Interrupt Notify Base Address' register points to the base address of the IC ESB pages and not to the notify page of the IC anymore as on P9. The 'Interrupt Notify Base Index' register is unused. This should improve overall performance. The P10 IC can handle higher interrupt rates compared to P9 and the PHB latency should be improved under ABT. Debug is easier as the interrupt number is now exposed on the PowerBUS. Signed-off-by: Cédric Le Goater <clg@kaod.org> [FB: port to phb4.c] Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06hw/phb5: Add support for PQ offloadingCédric Le Goater4-10/+80
The POWER9 DD2.0 introduced a StoreEOI operation which had benefits over the LoadEOI operation : less latency and improved performance for interrupt handling. Because of load vs. store ordering issues in some cases, it had to be deactivates. The POWER10 processor has a set of new features in the XIVE2 and the PHB5 controllers to address this problem. At the interrupt controller level, XIVE2 adds a new load offset to the ESB page which offers the capability to order loads after stores. It should be enforced by the OS when doing loads if StoreEOI is to be used. But this is not enough. The firmware should also carefully configure the PHB interrupt sources to make sure that operations on the PQ state bits of a source are routed to a single logic unit : the XIVE2 IC. The PHB5 introduces a new configuration PQ disable (bit 9) bit for this purpose. It disables the check of the PQ state bits when processing new MSI interrupts. When set, the PHB ignores its local PQ state bits and forwards unconditionally any MSI trigger to the XIVE2 interrupt controller. The XIVE2 IC knows from the trigger message that the PQ bits have not been checked and performs the check using the local PQ bits. This configuration bit only applies to MSIs and LSIs are still checked on the PHB to handle the assertion level. This requires a new XIVE interface to register a HW interrupt source using the IC ESB pages of the allocated HW interrupt numbers, and not the ESB pages of the HW source. This is what this change proposes for MSIs, LSI still being handled the old way. PQ disable is a requirement for StoreEOI. Signed-off-by: Cédric Le Goater <clg@kaod.org> [FB: port to phb4.c] Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06xive/p10: Add option flags to the XIVE exploitation modeCédric Le Goater1-7/+22
Change sligthly the semantic of the parameter of the opal_xive_reset() OPAL call to configure the interrupt mode of the machine and, at the same time, to configure the associated options. These options only apply to the XIVE exploitation mode. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06hw/phb5: Add initial supportJordan Niethe10-92/+217
The PHB5 logic on P10 is pretty close to the P9's version. So we keep our base phb4 implementation and just add the few changes within if statements. Signed-off-by: Jordan Niethe <jpn@ozlabs.au.ibm.com> [clg: misc cleanups and fixes ] Signed-off-by: Cédric Le Goater <clg@kaod.org> [Fixed compilation issue - Vasant] Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> [Nick: Unify PHB4/PHB5 drivers ] Signed-off-by: Nicholas Piggin <npiggin@gmail.com> [Mikey: set default lane eq settings for phb5] Signed-off-by: Michael Neuling <mikey@neuling.org> [FB: squash commits + small cleanup ] Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06psi/p10: Activate StoreEOICédric Le Goater2-1/+15
Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06psi/p10: Activate 64K ESB pagesCédric Le Goater2-5/+7
Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
generated by cgit v1.1 at 2025-09-19 06:26:44 +0000