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2017-07-28psr: occ: Add support to change power-shifting-ratioShilpasri G Bhat7-2/+319
Add support to set the CPU-GPU power shifting ratio which is used by the OCC power capping algorithm. PSR value of 100 takes all power away from CPU first and a PSR value of 0 caps GPU first. Documentation enhanced by Stewart Smith. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-28powercap: occ: Add a generic powercap frameworkShilpasri G Bhat7-4/+348
This patch adds a generic powercap framework and exports OCC powercap sensors using which system powercap can be set inband through OPAL-OCC command-response interface. Documentation for powercap enhanced by Stewart Smith. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-28opal-msg: Increase the max-async completion count by max chips possibleShilpasri G Bhat1-1/+1
OPAL-OCC command-response framework will also use async requests. So bump up the max-async completion requests to accommodate maximum number of chips possible. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-28occ: Add support for OPAL-OCC command/response interfaceShilpasri G Bhat2-4/+416
This patch adds support for a shared memory based command/response interface between OCC and OPAL. In HOMER, there is an OPAL command buffer and an OCC response buffer which is used to send inband commands to OCC. The OPAL-OCC command/response sequence is as follows: 1. Check if both 'OCC Progress' bit in OCC response flag and 'Cmd Ready' bit in OPAL command flag are set to zero. If yes then proceed with below steps to send a command to OCC. 2. Write the command value, request ID and command specific data to the OPAL command buffer. 3. Clear the response flag and set the 'Cmd Ready' bit in OPAL command flag to indicate command is ready. 4. OCC will poll the command flag every 4ms to check if 'Cmd Ready' bit is set by OPAL. If the bit is set then OCC will set the 'OCC Progress' bit. 5. OCC will process the command and write the response to the OCC response buffer and set the 'Rsp Ready' bit in the response flag and sends an interrupt. 8. OPAL will receive the interrupt and queue the response to the host. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Reviewed-by: Cyril Bur <cyril.bur@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-28phb4: Be more conservative on link presence timeoutMichael Neuling2-2/+3
In this patch we tuned our link timing to be more agressive: cf960e2884 phb4: Improve reset and link training timing Cards should take only 32ms but unfortunately we've seen some take up to 440ms. Hence bump our timer up to 1000ms. This can hurt boot times on systems where slots indicate a hotplug status but no electrical link is present (which we've seen). Since we have to wait 1 second between PERST and touching config space anyway, it shouldn't hurt too much. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-28phb4: Assert PERST before PHB resetMichael Neuling1-1/+6
Currently we don't assert PERST before issuing a PHB reset. This means any link issues while resetting the PHB will be logged as errors. This asserts PERST before we start resetting the PHB to avoid this. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-28Revert "phb4: Read PERST signal rather than assuming it's asserted"Michael Neuling1-3/+3
This reverts commit b42ff2b904165addf32e77679cebb94a08086966 The original patch assumes that PERST has been asserted well before (> 250ms) we hit here (ie. during hostboot). In a subesquent patch this will no longer be the case as we need to assert PERST during PHB reset, which may only be a few milliseconds before we hit this code. Hence revert this patch. Go back to the software mechanism using skip_perst to determine if PERST should be asserted or not. This allows us to keep the speed optimisation on boot. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-28phb4: Set REGB error enables based on link stateMichael Neuling1-2/+8
Currently we always set these enables when initing the PHB. If the link is already down, we shouldn't set them as it may cause spurious errors. This changes the code to only sets them if the link is up. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-28phb4: Mark PHB as fenced on cresetMichael Neuling1-1/+1
If we have to inject an error to trigger recover, we end up not marking the PHB as fenced in the PHB struct. This fixes that. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-28phb4: Clear errors before deasserting resetMichael Neuling1-0/+6
During reset we may have logged some errors (eg. due to the link going down). Hence before we deassert PERST or Hot Reset, we need to clear these errors. This ensures that once link training starts, only new errors are logged. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-28phb4: Split clearing REGB into new functionMichael Neuling1-5/+12
So others can call it. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-28phb4: Simplify calling phb4_eeh_dump_regs()Michael Neuling1-3/+5
Do verbose eeh check in phb4_eeh_dump_regs() rather than callers. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-28phb4: Simplify prepare_link_change() callsMichael Neuling1-8/+4
Just call phb4_prepare_link_change() rather than going through the slot ops. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-28phb4: Disable device config space access when fencedMichael Neuling1-0/+4
On DD2 you can't access device config space when fenced, so just disable access whenever we are fenced. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-28phb4: Clear more error registersMichael Neuling1-3/+9
Clears log and err1 registers. These are coming in the next spec. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-28phb4: Fix copy/paste typo in error loggingMichael Neuling1-1/+1
Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-28phb4: Dump devctl and devstat registersMichael Neuling1-0/+8
Dump devctl and devstat registers. These would have been useful when debugging the MPS issue. Suggested-by: Mike Perez <perezma@us.ibm.com> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-28phb4: Move functions around to avoid forward declarationsMichael Neuling1-133/+132
No code change Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-28phb4: Only clear some PHB config space registers on errorsMichael Neuling1-19/+32
Currently on error we clear the entire PHB config space. This is a problem as the PCIe Maximum Payload Size (MPS) negotiation may have already occurred. Clearing MPS in the PHB back to a default of 128 bytes will result an error for a device which already has a larger MPS configured. This will manifest itself as error due to a malformed TLP packet. ie. phbPblErrorStatus bit 41 = "Malformed TLP error" This has been seen after kexec on with some adapters. This fixes the problem by only clearing a subset of registers on a phb error. Reported-by: Rob Lippert <rlippert@google.com> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-25skiboot-5.7 release notesv5.7Stewart Smith1-0/+1508
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-25phb4: Add link training trace modeMichael Neuling2-0/+57
Add a mode to PHB4 to trace training process closely. This activates as soon as PERST is deasserted and produces human readable output of the process. This may increase training times since it duplicates some of the training code. This code has it's own simple checks for fence and timeout but will fall through to the default training code once done. Output produced, looks like the "TRACE:" lines below: [ 3.410799664,7] PHB#0001[0:1]: FRESET: Starts [ 3.410802000,7] PHB#0001[0:1]: FRESET: Prepare for link down [ 3.410806624,7] PHB#0001[0:1]: FRESET: Assert skipped [ 3.410808848,7] PHB#0001[0:1]: FRESET: Deassert [ 3.410812176,3] PHB#0001[0:1]: TRACE: 0x0000000101000000 0ms [ 3.417170176,3] PHB#0001[0:1]: TRACE: 0x0000100101000000 12ms presence [ 3.436289104,3] PHB#0001[0:1]: TRACE: 0x0000180101000000 49ms training [ 3.436373312,3] PHB#0001[0:1]: TRACE: 0x00001d0811000000 49ms trained [ 3.436420752,3] PHB#0001[0:1]: TRACE: Link trained. [ 3.436967856,7] PHB#0001[0:1]: LINK: Start polling [ 3.437482240,7] PHB#0001[0:1]: LINK: Electrical link detected [ 3.437996864,7] PHB#0001[0:1]: LINK: Link is up [ 4.438000048,7] PHB#0001[0:1]: LINK: Link is stable Enabled via nvram using: nvram -p ibm,skiboot --update-config pci-tracing=true Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-25phb4: Improve reset and link training timingMichael Neuling3-12/+110
This improves PHB reset and link training timing. Justifications and reasons are included in the patch. Polling frequencies are decreased from 100ms to 10ms. Added is a new state called PHB4_SLOT_LINK_STABLE which is now needed since the link training can be so fast that we touch config space too quickly (PCIe spec requires 1 second between PERST de-assert and device config space reads). We use this new state to sanity check the PHB and link before moving onto the PCI bus scan, where we no longer recover from these error conditions. Also added is simplified documentation of the PHB reset and training flow. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-25phb4: Add phb4_check_reg() to sanity check failuresMichael Neuling1-0/+17
This adds a function phb4_check_reg() to sanity check when we do MMIO reads from the PHB to make sure it's not fenced. This also adds some uses of this function in common locations where these may occur on PHB reset and link training. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-25phb4: Remove retry on electrical link timeoutMichael Neuling1-1/+1
Currently we retry if we don't detect an electrical link. This is pointless as all devices should respond in the given time. This patches removes this retry and just returns OPAL_HARDWARE if we don't detect an electrical link. This has the additional benefit of improving boot times on machines that have badly wired presence detect (ie. says a device is present when there isn't). Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-25phb4: Simplify calling phb4_retry_state()Michael Neuling1-10/+2
phb4_retry_state() returns a good error code, so just use that rather than complicating the caller. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-25phb4: Read PERST signal rather than assuming it's assertedMichael Neuling1-3/+3
Currently we assume on boot that PERST is asserted so that we can skip having to assert it ourselves. This instead reads the PERST status and determines if we need to assert it based on that. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-25phb4: Fix endian of TLP headers printMichael Neuling1-5/+5
Byte swap TLP headers so they are the same as the PCIe spec. Also remove redundant print. Suggested-by: Rob Lippert <rlippert@google.com> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-25phb4: Change timeouts prints to error levelMichael Neuling1-2/+2
If the link doesn't have a electrical link or the link doesn't train we should make that more obvious to the user. This boosts these prints to error level. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-25phb4: Better logs why the slot didn't workMichael Neuling1-1/+10
Better logs why the slot didn't work and make it a PR_ERR so users see it by default. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-25phb4: Force verbose EEH loggingMichael Neuling1-0/+2
Force verbose EEH. This is a heavy handed and we should turn if off later as things stabilise, but is useful for now. Signed-off-by: Michael Neuling <mikey@neuling.org> Acked-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-25phb4: Initialization sequence updatesRussell Currey1-13/+22
Mostly errata workarounds, some DD1 specific. The step Init_5 was moved to Init_16, so the numbering was updated to reflect this. (mikey: added section on ignoring errata ER20161123) Signed-off-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-25hdat/i2c: Fix array version checkOliver O'Halloran1-1/+1
We should be checking the array version, not the HDIF header version. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-25mem_region: Check for no-map in reserved nodesOliver O'Halloran1-1/+7
Regions with the no-map property should be handled seperately to "normal" firmware reservations. When creating mem_region regions from a reserved-memory DT node use the no-map property to select the right reservation type. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-25hdata/memory: Add newlines to debug messagesOliver O'Halloran1-2/+2
Missed a few. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-25hdata/memory: Add memory reservations to the DTOliver O'Halloran2-4/+55
Currently we just add these to a list of pre-boot reserved regions which is then converted into a the contents of the /reserved-memory/ node just before Skiboot jumps into the firmware kernel. This approach is insufficent because we need to add the ibm,prd-instance labels to the various hostboot reserved regions. To do this we want to create these resevation nodes inside the HDAT parser rather than having the mem_region flattening code handle it. On P8 systems Hostboot placed its memory reservations under the /ibm,hostboot/ node and this patch makes the HDAT parser do the same. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-25core/backtrace: Serialise printing backtracesOliver O'Halloran1-0/+12
Add a lock so that only one thread can print a backtrace at a time. This should prevent multiple threads from garbaling each other's backtraces. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-21FSP/CONSOLE: Do not enable input irq in write pathVasant Hegde1-3/+0
We use irq for reading input from console, but not in output path. Hence do not enable input irq in write path. Fixes : 583c8203 (fsp/console: Allocate irq for each hvc console) CC: Sam Mendoza-Jonas <sam@mendozajonas.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Acked-By: Samuel Mendoza-Jonas <sam@mendozajonas.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-20core/pci: Fix mem-leak on fast-rebootMatt Brown1-0/+1
Fast-reboot has a memory leak which causes the system to crash after about 250 fast-reboots. The patch fixes the memory leak. The cause of the leak was the pci_device's being freed, without freeing the pci_slot within it. Signed-off-by: Matt Brown <matthew.brown.dev@gmail.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-20travis: Add debian stretch and unstableStewart Smith3-0/+34
At the moment, we mark them both as being able to fail, as we're hitting an assert in one of the unit tests on debian stretch, and that hasn't yet been chased down. Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-20boot_tests: add PFLASH_TO_COPY for OpenBMCStewart Smith1-0/+6
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-19platform/witherspoon: Enable eSEL loggingVasant Hegde3-1/+7
OpenBMC stack added IPMI OEM extension to log eSEL events. Lets enable eSEL logging from OPAL side. See: https://github.com/openbmc/openpower-host-ipmi-oem/blob/d9296050bcece5c2eca5ede0932d944b0ced66c9/oemhandler.cpp#L142 (yes, that is the documentation) Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> [stewart@linux.vnet.ibm.com: remove pnor access request, add link to OpenBMC doc] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-19attrconst for testsStewart Smith9-9/+9
Fixes build warnings when running with higher optimization than -O0 Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-19gcov: properly handle gard and pflash code coverageStewart Smith2-2/+19
We end up with a bit of a nasty hack to count the libflash symlinks in gard and pflash as part of libflash code coverage, but it does work and is unlikely to break anytime soon. Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-19Makefile: gard/pflash targets for CI build with HOSTCFLAGS/HOSTGCOVFLAGSStewart Smith1-2/+2
This enables us to do coverage reports on gard/pflash. Reviewed-by: Cyril Bur <cyril.bur@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-19gard: enable building with -DDEBUG for ccan listStewart Smith1-1/+8
Reviewed-by: Cyril Bur <cyril.bur@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-19gard: enable building with skiboot HOSTCFLAGS warningsStewart Smith1-1/+21
Mostly unused parameter warnings due to callbacks Reviewed-by: Cyril Bur <cyril.bur@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-19pflash: include ccan/list/list.c to be able to build -DDEBUGStewart Smith1-1/+9
This enables some extra linked list checking Reviewed-by: Cyril Bur <cyril.bur@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-19pflash: build with skiboot HOSTCFLAGS warningsStewart Smith5-4/+13
mostly missing prototypes and unused parameters. Reviewed-by: Cyril Bur <cyril.bur@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-19pflash option to retrieve PNOR partition flagsMichael Tritz6-16/+167
This commit extends pflash with an option to retrieve and print information for a particular partition, including the content from "pflash -i" and a verbose list of set miscellaneous flags. -i option is also updated to print a short list of flags in addition to the ECC flag, with one character per flag. A test of the new option is included in libflash/test. Signed-off-by: Michael Tritz <mtritz@us.ibm.com> Reviewed-by: Cyril Bur <cyril.bur@au1.ibm.com> [stewart@linux.vnet.ibm.com: various test fixes, enable gcov] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-17skiboot: Fix comment around OPAL_IMC_COUNTERS_ enumMadhavan Srinivasan1-1/+1
Fixes: 7801be0fcf2a2 ('skiboot: Add opal calls to init/start/stop IMC devices) Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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