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2022-02-04external/mambo: Handle greater than 16 CPUsMichael Neuling1-1/+4
In OF mambo pads zeros in the CPU node names. So if you have more than 16 CPUs, the first core will be at /cpus/PowerPC@00. Currently we always look for /cpus/PowerPC@0. Fix by zero padding based on the max CPU count. This also converts to hex since that's what's actually needed. This fix should handle any topology. I've tested upto 128 threads (16 cores * 8 threads) but past that the mambo I have starts throwing internal errors. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-04Fix compilation waning "Missing #interrupt-cells"Abhishek Singh Tomar3-0/+27
Resolve : "Missing #interrupt-cells" warning duriing dts(device tree source) compilation hdata/test/p81-811.spira.dts:1434.37-1442.4: Warning (interrupt_provider): /interrupt-controller@3ffff80030000: Missing #interrupt-cells in interrupt provider An #interrupt-cells added to both reference dts for testing and source code to generate dtb from hdata. Signed-off-by: Abhishek Singh Tomar <abhishek@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-04Fix array-bound compilation warningsAbhishek Singh Tomar8-10/+29
Resolves : the warray bounds warning during compilation /build/libc/include/string.h:34:16: warning: '__builtin_memset' offset [0, 2097151] is out of the bounds [0, 0] [-Warray-bounds] 34 | #define memset __builtin_memset hw/fsp/fsp.c:1855:9: note: in expansion of macro 'memset' 1855 | memset(fsp_tce_table, 0, PSI_TCE_TABLE_SIZE); use volatile pointer to avoid optimization introduced with gcc-11 on constant address assignment to pointer. Signed-off-by: Abhishek Singh Tomar <abhishek@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-03platforms: put P8 platforms behind CONFIG_P8Stewart Smith2-5/+14
Shaves an additional 4kb off skiboot.lid.xz. Reviewed-by: Dan Horák <dan@danny.cz> Signed-off-by: Stewart Smith <stewart@flamingspork.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-03npu: Move npu.o and npu-hw-procedules.o under CONIFG_P8Stewart Smith2-1/+9
Make the P8 NPU code depend on CONFIG_P8. This requires converting a low level function to a no-op because the HMI NPU handling is not so cleanly layered. This saves an extra 6kb of skiboot.lid.xz. Reviewed-by: Dan Horák <dan@danny.cz> Signed-off-by: Stewart Smith <stewart@flamingspork.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-03hwprobe: convert vas_init(), nx_init()Stewart Smith3-6/+4
Convert VAS and NX to use the hwprobe facility for init. Reviewed-by: Dan Horák <dan@danny.cz> [npiggin: remove imc_init because it moved later in boot (fbcbd4e47c)] Signed-off-by: Stewart Smith <stewart@flamingspork.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-03hw/slw: split P8 specific code into its own fileNicholas Piggin11-493/+573
POWER8 support is large and significantly different than P9/10 code. This change prepares to make P8 support configurable. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> [ clg: Removed commented headers in slw.c ] Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-03hw/slw: Move P8 bits behind CONFIG_P8Nicholas Piggin5-88/+104
This saves about 10kB from skiboot.lid.xz Reviewed-by: Dan Horák <dan@danny.cz> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-03SBE: create processor-independent timer APIsNicholas Piggin10-36/+64
Rather than have code call processor-specific SBE routines depending on version, hide those details in SBE APIs. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> [ clg: Fixed run-timer test ] Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-03Add CONFIG_P8 with PHB3 behind itStewart Smith4-4/+29
We can use a base CPU of POWER9 if we don't have P8. We can also hide PHB3 code behind this, and shave 12kb off skiboot.lid.xz Reviewed-by: Dan Horák <dan@danny.cz> [npiggin: add cpp define, fail gracefully on P8] Signed-off-by: Stewart Smith <stewart@flamingspork.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-03hwprobe: convert PHB, NPU, PAU subsystems to hwprobeStewart Smith7-25/+14
Reviewed-by: Dan Horák <dan@danny.cz> [npiggin: split out from initial hwprobe pach] Signed-off-by: Stewart Smith <stewart@flamingspork.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-03Introduce hwprobe facility to avoid hard-coding probe functionsStewart Smith5-1/+118
hwprobe is a little system to have different hardware probing modules run in the dependency order they choose rather than hard coding that order in core/init.c. Reviewed-by: Dan Horák <dan@danny.cz> Signed-off-by: Stewart Smith <stewart@flamingspork.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-03fast-reboot: fix TLB cleanup after fast rebootNicholas Piggin1-0/+4
POWER9/10 are missing TLB flushing after fast reboot. Add it back to cpu_fast_reboot_complete(), which is where fast-reboot code thinks it should be. Suggested-by: Cédric Le Goater <clg@fr.ibm.com> Fixes: 53ef0db6e2 ("asm/head.S: set POWER9 radix HID bit at entry") Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-23core/cpu: move sleep/wake synchronisation out from low level codeNicholas Piggin1-110/+42
The sleep/wake synchronisation involes the waker setting a wake condition then testing if the target needs to be woken, vs setting a wake-required flag then testing the wake condition. The low level sleep state call comes after that. This patch moves the synchronisation out from the low level sleep functions and consolidates both copies into one place. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-23core/cpu: make cpu idle states simplerNicholas Piggin2-27/+53
Rework the CPU idle state code: * in_idle is true for any kind of idle including spinning. This is not used anywhere except for state assertions for now. * in_sleep is true for idle that requires an IPI to wake up. * in_job_sleep is true for in_sleep idle which is also cpu_wake_on_job. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-23core/cpu: move cpu_wake out of job_lockNicholas Piggin1-1/+2
There is no need to send the IPI while holding the job_lock. If the target does wake after the job is queued and before we send the IPI, it will check for new jobs anyway. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-23core/cpu: refactor IPI sendingNicholas Piggin1-18/+13
Pull the IPI sending code into its own function where it is used in two places. cpu_wake() already checks in_idle, so its caller does not need to check pm_enabled. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-23core/cpu: remove POWER8 IPI loopNicholas Piggin1-3/+1
POWER8 does not have to loop sending IPIs until the destination wakes up. cpu_wake() only sends IPI so that should be enough here too. This will help the next patch make a common IPI sending function. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-23core/cpu: rewrite idle synchronisationNicholas Piggin1-100/+156
Idle reconfiguration is difficult to follow and verify as correct because it can occur while CPUs are in low-level idle routines. For example pm_enabled can change while CPUs are idle. If nothing else, this can result in "cpu_idle_p9 called pm disabled" messages. This changes the idle reconfiuration to always kick all other CPUs out of idle code first whenever idle settings (pm_enabled, IPIs, sreset, etc.) are to be changed. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-23chiptod: properly zero TB SPR when cleaning up for invalid TBNicholas Piggin1-1/+2
The existing sequence writes TBU twice and leaves TBL unchanged. This may not really matter if it's being resynced from the chiptod soon, but it's possible it could clear a parity error. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-09secvar/pkcs7: fix a wrong sizeof()Daniel Axtens1-1/+1
This code isn't directly used by skiboot, but it is wrong and potentially insecure so I'm fixing it in case it's used in the future. We pass sizeof(hash) into mbedtls_pk_verify(). However, hash is a pointer, not an array, so rather than passing the length of the hash to verify we'll pass in 8, and only compare the first 8 bytes of the hash rather than all 32. Pass in 0 instead. That tells mbedtls to work out the length based on the hash type. We allocated enough memory for whatever hash type the PKCS#7 message declared so this will be safe. Signed-off-by: Daniel Axtens <dja@axtens.net> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-09libfdt: sync to upstream dtc.git commit 45f3d1a095ddNicholas Piggin19-889/+665
sync to upstream dtc.git commit 45f3d1a095dd ("libfdt: overlay: make overlay_get_target() public") from previous upstream sync commit 243176c ("Fix bogus error on rebuild"). This mainly updates license headers, fixes one or two small bugs, sign mismatches, integer overflow, and cases of undefined behaviour, compile warnings for newer compilers, and introduces some checking options (which might be useful to speed up fdt operations on awan). The recipe for this patch is: $ cp ../dtc/libfdt/* libfdt/ $ git add libfdt/fdt_check.c $ rm libfdt/meson.build Then add the INT32_MAX define to libc/include/limits.h, and update libfdt/Makefile.inc and libfdt/README.skiboot. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-09ccan: sync to upstream ccan.git commit ca7c5a9e04f3Nicholas Piggin62-199/+1055
sync to upstream ccan.git commit ca7c5a9e04f3 ("ccan: make tal_dump() format more regular."). The recipe used to sync upstream is: $ cd ccan $ ./tools/create-ccan-tree -b make tmp \ array_size check_type container_of heap \ short_types build_assert endian list str $ # replace directories in skiboot/ccan/ with those in tmp/ccan/ $ cd ../skiboot $ patch -p1 < ccan/skiboot.patch This also adds a README.skiboot to help with future updates. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-09hw/lpc: fix compilation errorNicholas Piggin1-0/+1
Compilation can fail when building tests if the opal-api.h include is not pulled in via headers. Include it directly. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-09ccan: switch list_add_before/after arguments to match upstreamNicholas Piggin5-11/+11
Upstream ccan uses (list, existing entry, new entry) parameter ordering rather than (list, new entry, existing entry) ordering. Switch these to make syncing with upstream simpler. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-11-10hdata: add mmu-pid-bits and mmu-lpid-bits for POWER10 CPUsNicholas Piggin2-0/+9
This adds ibm,mmu-pid-bits and a new ibm,mmu-lpid-bits to POWER10 CPUs. POWER9 Linux has some workarounds for processors bugs that means it's probably safer to not add the entries there. Linux already hard codes these values correctly on these processors, but this allows more flexibility to change things. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-11-10test/qemu: Add PCI devicesCédric Le Goater1-2/+20
This defines a PCI layout close to an OpenPOWER system and adds an optional disk to boot from. Fix verbose runs while we are at it. Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-11-10CI: Update runs with P10 mamboCédric Le Goater8-1/+8
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-11-10CI: Update centos8 runs with P8 and P9 mamboCédric Le Goater1-0/+2
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-11-05CI: Remove travis config fileFrederic Barrat1-71/+0
travis.org is dead. Using travis-ci.com has some money implication and we won't be able to check whether the config is still valid and the tests passing. We migrated most of the existing CI on travis to github actions. So this can only bit-rot so let's remove it. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-11-05CI: Clean up some Docker filesFrederic Barrat5-11/+8
Miscellaneous cleanup in the Docker files, mostly removing unneeded packages. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-11-05CI: Small cleanup in the github actions workflow fileFrederic Barrat1-3/+10
Strengthen the container security settings, since we don't seem to need more. The rest of the patch is cosmectic. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-11-05CI: Rename ubuntu-latest to ubuntu-rollingFrederic Barrat4-15/+14
In the docker world, ubuntu-latest is the latest LTS release, 20.04 as of this writing. ubuntu-rolling is the latest (non-devel) release, which is 21.10 as of this writing. So rename our CI files accordingly to avoid confusion. Also ubuntu 21.10 ships with a recent enough qemu-system-ppc package so we can now run a simple qemu boot test for powernv. The Docker file fetches a kernel image from the op-build repo on github. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-11-05CI: Add Fedora 35 to github actionsFrederic Barrat3-1/+33
The only change with Fedora 34 is that since the qemu-system-ppc package is recent, we can now run the qemu boot test. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-11-05test/qemu: Fix testFrederic Barrat1-1/+2
Fix a syntax error in the expect script. Add -nographic when starting qemu to avoid problems on systems where gtk is installed. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-11-05README: Update path to fetch a kernel imageFrederic Barrat1-1/+1
openpower.xyz no longer exists but op-build now exports artifacts on github. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-11-04secvar/edk2: store timestamp variable in protected storageEric Richter2-1/+4
Each signed variable update contains a timestamp -- this timestamp is checked against the previous timestamp seen for that particular variable (if any), and the update is rejected if the timestamp is not a later time than the previous. This timestamp check is intended to prevent re-use of signed update files. Currently, the code stores the timestamps in the TS variable, which is then stored in regular variable storage (typically PNOR). This patch promotes the variable to "protected storage" (typically TPM NV), so avoid this variable being accidentally cleared. This change should only come into effect when either: - initializing secvar for the first time (i.e. first boot, or after a key-clear-request) - processing any variable update Systems that already have a TS variable in PNOR will not be affected until either of the above actions are taken. Signed-off-by: Eric Richter <erichte@linux.ibm.com> Tested-by: Nick Child <nick.child@ibm.com> Reviewed-by: Daniel Axtens <dja@axtens.net> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-11-04secvar/secboot_tpm: unify behavior for bank hash check and secboot header checkEric Richter2-16/+29
As the PNOR variable space cannot be locked, the data must be integrity checked when loaded to ensure it has not beeen modified by an unauthorized party. In the event that a modification has been detected (i.e. hash mismatch), we must not load in data that could potentially be compromised. However, the previous code was a bit overzealous with its reaction to detecting a compromised SECBOOT partition, and also had some inconsistencies in behavior. Case 1: SECBOOT partition cleared. .init() checks the header for the magic number and version. As neither matches, will reformat the entire partition. Now, .load_bank() will pass, as the data was just freshly reformatted (note: this also could trigger the bug addressed in the previous patch). Only variables in the TPM will be loaded by .load_bank() as the data in SECBOOT is now empty. Case 2: Bank hash mismatch. .load_bank() panics and returns an error code, causing secvar_main() to jump to the error scenario, which prevents the secvar API from being exposed. os-secure-enforcing is set unconditionally, and the user will have no API to manage or attempt to fix their system without issuing a key clear request. This patch unifies the behavior of both of these cases. Now, .init() handles checking the header AND comparing the bank hash. If either check fails, the SECBOOT partition will be reformatted. Variables in the TPM will still be loaded in the .load_bank() step, and provided the backend stores its secure boot state in the TPM, secure boot state can be preserved. Signed-off-by: Eric Richter <erichte@linux.ibm.com> Tested-by: Nick Child <nick.child@ibm.com> Reviewed-by: Daniel Axtens <dja@axtens.net> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-11-04secvar/secboot_tpm: correctly reset the control index on secboot formatEric Richter1-4/+7
When the SECBOOT partition is formatted, the bank hash stored in the control TPM NV index must be updated to match, or else we will immediately fail to load the freshly formatted data at the .load_bank() step. However, while the secboot_format() function does calculate and update the bank hash, it only writes the new hash for bank 0. It does not update the value for bank 1, or set the current active bank. This works as expected if the active bank bit happens to be set to 0. On the other hand, if the active bit is set to 1, the freshly formatted bank 1 will be compared against the unchanged bank hash in bank 1 at the load step, therefore causing an error. This patch fixes this issue by also setting the active bit to 0 to match the freshly calculated hash. Signed-off-by: Eric Richter <erichte@linux.ibm.com> Tested-by: Nick Child <nick.child@ibm.com> Reviewed-by: Daniel Axtens <dja@axtens.net> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-11-03skiboot.lds.S: add DWARF v5 sectionsCédric Le Goater1-2/+4
This fixes "orphan section" warnings when linking skiboot. Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-11-03CI: start using github actionsFrederic Barrat5-0/+91
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-10-26skiboot v7.0 release notesv7.0Vasant Hegde1-0/+28
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-26opal-api: Drop diagnostics data type symbol for PHB5Frederic Barrat1-1/+0
All PHB5 error registers read when getting the PHB diagnostics data have the exact same definitions as on PHB4, so we don't need any new type. OPAL_PHB_ERROR_DATA_TYPE_PHB5 is not used in skiboot. It's never been imported on linux, so it is safe to remove the symbol. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-26skiboot v6.8.1 release notesVasant Hegde1-0/+31
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-26skiboot v6.6.6 release notesCédric Le Goater1-0/+15
Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-26skiboot v6.7.3 release notesVasant Hegde1-0/+29
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-26skiboot v6.0.24 release notesFrederic Barrat1-0/+22
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-21xive/p10:: Declare xive2 DT node as an interrupt-controllerFrederic Barrat1-1/+6
This patch fixes errors seen when linux looks for the interrupt to use for a device LSI: pci X:Y:Z of_irq_parse_pci: failed with rc=-22 The of/irq parsing code requires those new properties to be able to map the interrupt specifier correctly. It was not needed before comitting cd12ea6d8e1 ("interrupts: Do not advertise XICS support on P10"), because the LSI mapping code was defaulting to the XICS interrupt controller node, which is now removed (and had those properties). Fixes: cd12ea6d8e1 ("interrupts: Do not advertise XICS support on P10") Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19pau: Add support for OpenCAPI Persistent Memory devices.Christophe Lombard7-16/+152
Lowest Point of Coherency (LPC) memory allows the host to access memory on an OpenCAPI device. When the P10 chip accesses memory addresses on the AFU, the Real Address on the PowerBus must hit a BAR in the PAU such as GPU-Memory BAR. The BAR defines the range of Real Addresses that represent AFU memory. The two existing OPAL calls, OPAL_NPU_MEM_ALLOC and OPAL_NPU_MEM_RELEASE are used to manage the AFU momory. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19pau: mmio invalidatesChristophe Lombard4-0/+49
The remaining translation mode: OpenCAPI 5.0 with TLBI/SLBI Snooping, is not used due to performance problems caused by the mismatch between the ERAT and Bloom Filter sizes. When the Address Translation Mode requires TLB and SLB Invalidate operations to be initiated using MMIO registers, a set of registers like the following is used: • XTS MMIO ATSD0 LPARID register • XTS MMIO ATSD0 AVA register • XTS MMIO ATSD0 launch register, write access initiates a shoot down • XTS MMIO ATSD0 status register Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
generated by cgit v1.1 at 2024-08-02 19:17:32 +0000