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2019-08-15MPIPL: Add support to trigger MPIPL on BMC systemVasant Hegde3-3/+84
On FSP based system we call 'attn' instruction. FSP detects attention and initiates memory preserving IPL. On BMC system we have to call SBE S0 interrupt to initiate memory preserving IPL. This patch adds support to call SBE S0 interrupt in assert path. Sequence : - S0 interrupt on secondary chip SBE - S0 interrupt on primary chip SBE Note that this is hooked to ipmi_terminate path. We have HDAT flag for MPIPL support. If MPIPL is not supported then we don't create 'ibm,opal/dump' node and we will fall back to existing termination flow. Finally we want to log error log to BMC before triggerring MPIPL. Hence this patch re-organizes ipmi_terminate() such that we call ipmi_log_terminate_event() before triggering MPIPL. Note: - At present we do not have a proper way to detect SBE is alive or not. So we wait for predefined time and then call normal reboot. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> [oliver: rebased] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-15SBE: Send OPAL relocated base address to SBEVasant Hegde3-0/+58
OPAL relocates itself during boot. During memory preserving IPL hostboot needs to access relocated OPAL base address to get MDST, MDDT tables. Hence send relocated base address to SBE via 'stash MPIPL config' chip-op. During next IPL SBE will send stashed data to hostboot... so that hostboot can access these data. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> [oliver: rebased] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-15MPIPL: Add OPAL API to register tagsVasant Hegde2-1/+41
This patch adds new API to register tags. opal_mpipl_register_tag(enum opal_mpipl_tags tag, uint64_t tag_val) tag: OPAL_MPIPL_TAG_KERNEL During first boot, kernel will setup its metadata area and asks OPAL to preserve metadata area pointer across MPIPL. Post MPIPL kernel requests OPAL to provide metadata pointer and it will use that pointer to retrieve metadata and create dump. OPAL_MPIPL_TAG_BOOT_MEM During MPIPL registration kernel will specify how much memory firmware can use for Post MPIPL load. Post MPIPL petitboot kernel will query for this tag to get boot memory size. Return values: OPAL_SUCCESS : Operation success OPAL_PARAMETER : Payload passed invalid tag Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> [oliver: rebased] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-15MPIPL: Add OPAL API to register for dump regionVasant Hegde3-1/+192
This patch add new API to register for dump region. u64 opal_mpipl_update(u8 ops, u64 src, u64 dest, u64 size) ops : OPAL_MPIPL_ADD_RANGE Add new entry to MPIPL table. Kernel will send src, dest and size. During MPIPL content from source address is moved to destination address. src = Source start address dest = Destination start address size = size OPAL_MPIPL_REMOVE_RANGE Remove kernel requested entry from MPIPL table. src = Source start address dest = Destination start address size = ignore OPAL_MPIPL_REMOVE_ALL Remove all kernel passed entry from MPIPL table. src = ignore dest = ignore size = ignore OPAL_MPIPL_FREE_PRESERVED_MEMORY Post MPIPL, kernel will indicate OPAL that it has processed dump and it can clear/release metadata area. src = ignore dest = ignore size = ignore Return values: OPAL_SUCCESS : Operation success OPAL_PARAMETER : Payload passed invalid data OPAL_RESOURCE : Ran out of MDST or MDDT table size OPAL_HARDWARE : MPIPL not supported Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> [oliver: rebased] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-15MPIPL: Define OPAL metadata areaVasant Hegde3-1/+30
We want to save some information (like crashing CPU PIR, kernel tags, etc) before triggering MPIPL. Post MPIPL we will use this information to retrieve dump metadata and create dump. MDRT table doesn't need 64K. Hence split MDRT table to accommodate metadata area. Finally define metadata structure. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> [oliver: rebased] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-15MPIPL: Register for OPAL dumpVasant Hegde4-1/+153
This patch adds support to register for OPAL dump. - Calculate memory required to capture OPAL dump - Reserve OPAL dump destination memory - Add OPAL dump details to MDST and MDDT table Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> [oliver: rebased] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-15hdata: Create /ibm, opal/dump device tree nodeVasant Hegde2-0/+22
We use MPIPL system parameter to detect whether MPIPL is supported or not. If its supported create new device tree node (/ibm,opal/dump) to pass all dump related information to kernel. This patch creates new node and populates below properties: - compatible - dump version (ibm,opal-dump) - fw-load-area - Memory used by OPAL to load kernel/initrd from PNOR (KERNEL_LOAD_BASE & INITRAMFS_LOAD_BASE). This is the temporary memory used by OPAL during boot. Later Linux kernel is free to use this memory. During MPIPL boot also OPAL will overwrite this memory. OPAL will advertise these memory details to kernel. If kernel is using these memory and needs these memory content for proper dump creation, then it has to reserve destination memory to preserve these memory ranges. Also kernel should pass this detail during registration. During MPIPL firmware will take care of preserving memory and post MPIPL kernel can create proper dump. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> [oliver: rebased] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-15hdata: Adjust various structure offset after relocationVasant Hegde1-0/+23
ntuple addresses in SPIRAH are relative to payload base. Update various addresses after relocation so that hostboot can access new address to capture dump. Note that we update relocated SPIRAH. So future if we add early OPAL crash support, hostboot can still collect dump using origianl skiboot base. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> [oliver: rebased] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-15hdata: Update spirah structureVasant Hegde1-3/+24
Update MDST, MDDT and MDRT ntuple inside SPIRAH. During MPIPL hostboot will use these details to preserve memory. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> [oliver: rebased] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-15mem-map: Setup memory for MDRT tableVasant Hegde1-1/+7
Hostboot fills MDRT table after moving memory content from source to destination memory. And OPAL relies on this table to extract the dump. We have to make sure this table is intact. Hence define memory relative to SKIBOOT_BASE so that our relocation doesn't overwrite this memory. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> [oliver: rebased] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-15mem-map: Setup memory for MDDT tableVasant Hegde2-4/+11
Each entry in MDST and MDDT takes 16 bytes. With 1K we can have upto 64 entries. This is sufficient to support OPAL MPIPL (memory preserving IPL). Presently OPAL reserves 2K memory for MDST table. Lets split this into two region of 1K for MDST and MDDT table. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> [oliver: rebased] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-15hdata: Define various DUMP related structuresVasant Hegde3-1/+70
- MDDT is used by OPAL to pass destination memory details to hostboot. - MDRT is used by hostboot to pass post dump result table to OPAL. - Processor dump area is used to capture architected register data. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> [oliver: rebased] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-15hdata: Split MDST 'type' field to accommodate MPIPLVasant Hegde3-11/+21
The MPIPL facility needs to store region and type information corresponding with each MDST entry. - data region : dump data regions (like DUMP_REGION_* ) - dump type : Reflects MDST entry usage (used by SYSDUMP -OR- FADUMP) The existing type field is currently not used by FSP and/or firmware, so it is safe to re-purpose it. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> [oliver: rebased] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-15FSP/MDST: Rename fsp-mdst-table.c -> fsp-sysdump.cVasant Hegde4-12/+12
MDST is a ntuple inside SPIRAH. Its just a interface to pass memory ranges to be captured as part of dump to FSP/Hostboot. Today OPAL is using MDST ntuple to pass list of memory region (mostly OPAL console and host dmesg) to be collected as part of SYSDUMP. Soon we are going to support OPAL MPIPL feature (aka Memory Preserving IPL). Even MPIPL uses MDST/MDDT table. Hence rename files based on feature instead of some table name: - fsp-mdst-table.c -> fsp-sysdump.c - fsp-mdst-table.h -> opal-dump.h (This will cater both SYSDUMP and MPIPL) - Rename structure -> dump_mdst_table -> mdst_table This patch does renaming and header file adjustment. No functionality changes. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> [oliver: rebased] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-15OPAL: Add OPAL boot entry address to device treeVasant Hegde1-0/+2
Needed for creating OPAL core file. Sample output: -------------- sys/firmware/devicetree/base/ibm,opal # lsprop ... opal-boot-address 00000000 30002560 ... Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> [oliver: rebased] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-02SPDX fixups and Copyright date fixesStewart Smith30-21/+52
Ensure the (C) who and years are correct, based on git history. Also a few SPDX fixups Signed-off-by: Stewart Smith <stewart@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-02doc/device-tree/ibm, opal/firmware/version: clarify timeline of git-id vs ↵Stewart Smith1-2/+6
version Signed-off-by: Stewart Smith <stewart@linux.ibm.com> Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-02doc/requirements.txt: pin docutils at 0.14Stewart Smith1-0/+2
docutils is a dependency for sphinx. The recently released 0.15 version throws a syntax error like so: + cd doc + make html sphinx-build -b html -d _build/doctrees . _build/html Traceback (most recent call last): File "/usr/bin/sphinx-build", line 6, in <module> from sphinx.cmd.build import main File "/usr/lib64/python2.7/site-packages/sphinx/cmd/build.py", line 20, in <module> from docutils.utils import SystemMessage File "/usr/lib/python2.7/site-packages/docutils/utils/__init__.py", line 21, in <module> import docutils.io File "/usr/lib/python2.7/site-packages/docutils/io.py", line 348 (self.destination.mode, mode)), file=self._stderr) ^ SyntaxError: invalid syntax make: *** [Makefile:53: html] Error 1 obviously, this isn't ideal - so let's pin our version to one that actually works. Signed-off-by: Stewart Smith <stewart@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-02occ: Add pstate corresponding to base frequency to DTShilpasri G Bhat2-1/+13
Unlike POWER8, nominal frequency is not the highest guaranteed frequency of the POWER9 chip. In POWER9, the highest guaranteed frequency is greater than the nominal frequency and is referred to as base frequency. In POWER9 base frequency is the highest frequency the processor will operate at when ALL cores are active and in ANY operating condition. This patch exports the turbo pstate as the base frequency as per OCC documentation. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> [oliver: delete ibm,pstate-base on fast reboot] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-02errorlog: Prevent alignment error building with gcc9.Michal Suchanek1-1/+1
Fixes this build error: [ 52s] hw/fsp/fsp-elog-write.c: In function 'opal_elog_read': [ 52s] hw/fsp/fsp-elog-write.c:213:12: error: taking address of packed member of 'struct errorlog' may result in an unaligned pointer value [-Werror=address-of-packed-member] [ 52s] 213 | list_del(&log_data->link); [ 52s] | ^~~~~~~~~~~~~~~ Fixes: https://github.com/open-power/skiboot/issues/247 Signed-off-by: Michal Suchanek <msuchanek@suse.de> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-02hw/sbe-p9: Fix multi-line log messagesOliver O'Halloran1-3/+3
When sending messages to the SBE we log the message using a multi-line log message that looks like this: [ 96.390873752,8] SBE: Message queued [chip id = 0x0]: Reg0 : 000002010054d401 Reg1 : 0000000000030d40 Reg2 : 0000000000000000 Reg3 : 0000000000000000 The lack of a common prefix makes the log messages annoying to deal with since you can just grep for SBE: to get all the SBE related messages, and you can't use grep -v to remove them. There's no real benifit to squashing all this into a single prlog() call, so use a for loop to print the registers. With this patch the output is: [ 93.253511545,8] SBE: Message queued [chip id = 0x0]: [ 93.253512343,8] SBE: Reg0 : 000002010059d401 [ 93.253513167,8] SBE: Reg1 : 0000000000030d40 [ 93.253513894,8] SBE: Reg2 : 0000000000000000 [ 93.253514627,8] SBE: Reg3 : 0000000000000000 Cc: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Acked-by: Stewart Smith <stewart@linux.ibm.com> Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2019-08-02core/pci-quirk: Microsemi switch UR workaroundOliver O'Halloran3-0/+90
Some Microsemi switches have a bug where accessing an unimplemented config space register causes an Unsupported Request error. This is a violation of the PCI spec which requires devices to ignore writes and return 0x00 when an unimplemented config space register is accessed. Linux allows userspace to access all of config space and tools (e.g. lspci) will read the entire 4KB space. This results in flood of spurious EEH events since POWER chips treat URs as an indication of a malfunctioning device. This patch adds a PCI device quirk that scans the config space of the switch in early boot to determine what ranges will trigger a UR. With this information we can then use config filters to block accesses to the problematic ranges. This scanning process is a little slow, but: a) This bug should be resolved by a switch firmware update eventually, and b) System firmware updates might result PCIe capabilities being added or removed from the switch's config space. This means that we would have a cache invalidation problem which isn't straightforward to resolve. We can check if the workaround is needed at all by reading 0xFF (the end of the legacy config space) since we know the switch never has anything implemented for that address. Do the simple thing for now rather than trying to make it faster since this should be a temporary workaround. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Reviewed-By: Alistair Popple <alistair@popple.id.au>
2019-08-02core/pci: Export pci_check_clear_freeze()Oliver O'Halloran2-5/+12
We'd like to be able to check when we get a freeze in the quirk handling code. Make pci_check_clear_freeze un-static so it can be used elsewhere. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Reviewed-By: Alistair Popple <alistair@popple.id.au>
2019-08-02core/pci-quirk: Re-order struct membersOliver O'Halloran3-5/+5
Having the function first throws out the alignment on the VDID since the functions names are probably different lengths. Swap them ordering of the struct members so the VDID comes first to keep things tidy. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Reviewed-by: Stewart Smith <stewart@linux.ibm.com> Reviewed-by: Alistair Popple <alistair@popple.id.au>
2019-07-30Support BMC IPMI heartbeat commandAndrew Geissler1-0/+14
A few years ago, the OpenBMC code added support for a "heartbeat" command to send to the host. This command is used after the BMC is reset to check if the host is running. Support was never added to the host side however so currently when the BMC sends this command, this appears in the host console: IPMI: unknown OEM SEL command ff received There is no response needed by the host (other then the low level acknowledge of the command which already occurs). This commit handles the command so the error is no longer printed (does nothing with the command though since no action is needed). Here's the tested output of this patch in the host console (with debug enabled): IPMI: BMC issued heartbeat command: 00 Signed-off-by: Andrew Geissler <geissonator@yahoo.com>
2019-07-30hw: Put SPDX on new filesOliver O'Halloran6-84/+18
Convert the npu3 files to use SPDX headers. Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-07-26Makefiles: Remove --Wno-stringop-truncationOliver O'Halloran1-1/+0
To disable a warning you use the command line parameter: -Wno-<warning-name>, not --Wno-<warning-name> GCC seems to ignore parameters starting with a double dash, so we've been building with the stringop-trunction warning enabled for about a year now and no one has complained. Away it goes. Fixes: cd2b103f2488 ("Makefile: Check -Wno-stringop-truncation is supported") Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-07-26travis: do gcov builds on fedora30Stewart Smith1-5/+3
We've fixed up gcov for newer GCC. Signed-off-by: Stewart Smith <stewart@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-07-26travis: remove fedora29Stewart Smith5-42/+31
No need to keep old Fedora releases around. Signed-off-by: Stewart Smith <stewart@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-07-26travis: Enable fedora30 for ppc64leStewart Smith1-2/+0
Back in ac734a084319 when we added fedora30, we were seeing weird failures on ppc64le. We no longer see them, so enforce fedora30 passing there. Signed-off-by: Stewart Smith <stewart@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-07-26asm/head: set skiboot TOC in interrupt handler entryNicholas Piggin1-3/+5
Some code runs with r2 not set to the skiboot TOC, for example the secureboot CVC (see call_rom_entry). If a system reset or machine check is taken at this time, the skiboot interrupt handler will crash badly rather than report it. So set the skiboot TOC into r2 in the interrupt entry code. r2 is already saved and restored, so in the case of recoverable exceptions, this will restore the correct r2 when returning to such code. This issue was found by Stewart, and this patch is based on his initial fix, with some modification. Cc: Stewart Smith <stewart@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-07-26Add Swift platformReza Arbab2-1/+142
Swift is a dual-chip Axone system, wired for four possible GPUs. This is akin to a POWER9P version of a (Redbud) Witherspoon. Add a platform definition for this system, using details from v1.1 of the design workbook (29 May 2019). Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-07-26hw: Introduce npu3Reza Arbab12-10/+3667
POWER9P systems have been upgraded with NVLink 3.0 interconnects. The underlying hardware is fundamentally different--each POWER9 chip has (1 NPU) * (3 stacks) * (2 bricks) = (6 links) Where in each POWER9P chip, there are (3 NPUs) * (4 bricks) = (12 links) This flatter hierarchy simplifies the firmware implementation a bit, but also prevents sharing much common code with npu2. As in previous versions, initialize the hardware and expose each link to the OS as a virtual PCIe device. This initial support covers NVLink devices only, with OpenCAPI to follow. Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Reviewed-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-07-26npu2: Add checks to npu2-only codepathsReza Arbab3-3/+11
To prepare for npu3, add a few checks in codepaths that are only for npu2. Compare against PVR_TYPE_P9, as npu3 will be in systems of PVR_TYPE_P9P (or greater). Alternatively, check for dt compatibility with "ibm,power9-npu" because npu3 will use "ibm,power9-npu3". Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-07-26npu2: Refactor NPU OPAL callsReza Arbab4-132/+191
Abstract the OPAL entry points for npu2, moving them to a new file. This prepares us to add parallel npu3 versions of the same APIs. No functional change. Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-07-26npu2: Prepare purge_l2_l3_caches() for reuseReza Arbab5-152/+197
Move this to a separate compilation unit with its own header, for reuse. The code formerly in npu2.c is copied verbatim. The #defines formerly in npu2-regs.h have been reformatted and changed to use PPC_BITMASK() instead of multiple consecutive PPC_BIT()s. Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com> Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Stewart Smith <stewart@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-07-26hw/phys-map: Add Axone memory mapReza Arbab3-3/+141
Add the physical memory map for Axone systems. According to 'make hw-check', there are no holes or overlapping regions. Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Acked-by: Michael Neuling <mikey@neuling.org> Reviewed-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com> Acked-by: Stewart Smith <stewart@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-07-26hw/phys-map: Add pvr argument to phys_map_init()Reza Arbab5-8/+16
When new chip types are added, phys_map_init() will need to know which memory map it should use. Instead of directly checking PVR, make it an argument to the function, so that 'make hw-check' can test all the maps. Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Acked-by: Michael Neuling <mikey@neuling.org> Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com> Acked-by: Stewart Smith <stewart@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-07-26Dedup $(HW_OBJS)Reza Arbab1-4/+2
How did I notice one dup in aa56d9a2abdb ("Remove duplicate npu-common.o from $(HW_OBJS)"), but not the other five? Remove them too. Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Reviewed-by: Alistair Popple <alistair@popple.id.au> Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-07-26SPDX-ify all skiboot codeStewart Smith469-5959/+1418
Use Software Package Data Exchange (SPDX) to indicate license for each file that is unique to skiboot. At the same time, ensure the (C) who and years are correct. See https://spdx.org/ Signed-off-by: Stewart Smith <stewart@linux.ibm.com> [oliver: Added a few missing files] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-07-26gard: fix installation ruleDan Horák1-2/+2
Use $(EXE) for the binary name instead of hard-coding. This completes the "gard: Use consistent name" change from commit 41109e5073bd ("gard: Use consistent name") Fixes: 41109e5073bd ("gard: Use consistent name") Signed-off-by: Dan Horák <dan@danny.cz> [oliver: prefix in title, fixes tag] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-07-23Updating shared constants for HBRTDan Crowell1-2/+69
Updated a few sets of constants for HBRT operation based on the most recent Hostboot implementation. - added all of the PIB return codes in for scom - added return cords for firmware_request and wakeup - added capability for 'clear all wakeups' Signed-off-by: Dan Crowell <dcrowell@us.ibm.com>
2019-07-19pci-slot: Allow to create slot for downstream port of any switchIlya Kuznetsov1-7/+2
System vendor may build systems with large PCIe tree with deeper switch topologies. Currenlty downstream ports slot creation is limited to first switch. Patch allows to use any. Signed-off-by: Ilya Kuznetsov <ilya@yadro.com> [oliver: added pci-slot prefix] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-07-19Move ec/ code to Rhesus platformStewart Smith8-20/+3
The embedded controller that Rhesus uses is exclusive to that platform, make it purely part of tha platform Signed-off-by: Stewart Smith <stewart@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-07-19xscom-utils: refer only objects not sources for getscomDan Horák1-1/+1
The rule for getscom binary should depend on object files only, not sources. Signed-off-by: Dan Horák <dan@danny.cz> Signed-off-by: Than Ngo <than@redhat.com> Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Reviewed-by: Stewart Smith <stewart@linux.ibm.com> [oliver: added xscom-utils prefix to subject] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-07-19gcov: Fix skiboot size to dump out from simulatorsStewart Smith3-3/+3
We can be up to 5MB now, and have been for a while. Fixes: 7c9b3eb3c149843a27b9674e66b0227cf289a29a Signed-off-by: Stewart Smith <stewart@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-07-19sparse: libstb/container: fix endian type for magic numberStewart Smith1-1/+1
libstb/container.c:38:28: warning: incorrect type in argument 1 (different base types) libstb/container.c:38:28: expected restricted beint32_t [usertype] be_val libstb/container.c:38:28: got unsigned int [usertype] Signed-off-by: Stewart Smith <stewart@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-07-19sparse: hdata/spira sw_xstop_fir_bitpos is uint8_t, has no endianStewart Smith2-3/+3
hdata/spira.c:625:33: warning: incorrect type in argument 1 (different base types) hdata/spira.c:625:33: expected restricted beint32_t [usertype] be_val hdata/spira.c:625:33: got unsigned char [usertype] fir_bit hdata/spira.c:625:33: warning: incorrect type in argument 1 (different base types) hdata/spira.c:625:33: expected restricted beint32_t [usertype] be_val hdata/spira.c:625:33: got unsigned char [usertype] fir_bit Signed-off-by: Stewart Smith <stewart@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-07-19sparse: hdata/iohub: correctly convert endiannessStewart Smith1-1/+1
hdata/iohub.c:723:22: warning: restricted beint16_t degrades to integer Signed-off-by: Stewart Smith <stewart@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-07-19sparse: hdata/fsp: u8 doesn't have endianStewart Smith2-2/+2
hdata/fsp.c:271:9: warning: incorrect type in argument 1 (different base types) hdata/fsp.c:271:9: expected restricted beint32_t [usertype] be_val hdata/fsp.c:271:9: got unsigned char const [usertype] uart_int_number hdata/fsp.c:271:9: warning: incorrect type in argument 1 (different base types) hdata/fsp.c:271:9: expected restricted beint32_t [usertype] be_val hdata/fsp.c:271:9: got unsigned char const [usertype] uart_int_number Signed-off-by: Stewart Smith <stewart@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
generated by cgit v1.1 at 2024-08-03 01:27:09 +0000