aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2017-06-26lpc: Enable "new" SerIRQ modeBenjamin Herrenschmidt1-1/+9
So we don't have to clear the bits on EOI manually. This works in conjunction with the DD2 test in psi.c Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-26psi: Use phys_map to setup the BARsBenjamin Herrenschmidt3-33/+23
Removes the hard coded address and the useless warning Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-26hdat/vpd: Don't warn and don't create a dummy "model-name"Benjamin Herrenschmidt1-3/+0
If the model property doesn't contain a known model number that we can translate into a name, assume it's already a name, stop warning and don't create an extraneous property. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-26phb4: Mask out write-1-to-clear registers in RC cfgRussell Currey1-5/+39
The root complex config space only supports 4-byte accesses. Thus, when the client requests a smaller size write, we do a read-modify-write to the register. However, some register have bits defined as "write 1 to clear". If we do a RMW cycles on such a register and such bits are 1 in the part that the client doesn't intend to modify, we will accidentally write back those 1's and clear the corresponding bit. This avoids it by masking out those magic bits from the "old" value read from the register. Signed-off-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-26phb4: Properly mask out link down errors during resetRussell Currey1-7/+20
Signed-off-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-26phb3/4: Silence a useless warningBenjamin Herrenschmidt2-2/+2
PHB's don't have base location codes on non-FSP systems and it's normal. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-26phb3/4: Move IO VPD preload out to a common placeBenjamin Herrenschmidt5-24/+13
The code is duplicated between phb3 and phb4 for no reason Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> # Conflicts: # core/init.c # hw/phb3.c Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-26phb4: Workaround bug in spec 053Benjamin Herrenschmidt1-2/+5
Wait for DLP PGRESET to clear *after* lifting the PCIe core reset Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-26phb4: DD2.0 updatesBenjamin Herrenschmidt3-119/+261
Support StoreEOI, full complements of PEs (twice as big TVT) and other updates. Also renumber init steps to match spec 063 Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-26xive: DD2.0 updatesBenjamin Herrenschmidt2-8/+55
Add support for StoreEOI, fix StoreEOI MMIO offset in ESB page, and other cleanups Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-26capp: Fix hang when CAPP microcode LID is missing on FSP machineBenjamin Herrenschmidt1-1/+3
When the LID is absent, we fail early with an error from start_preload_resource. In that case, capp_ucode_info.load_result isn't set properly causing a subsequent capp_lid_download() to call wait_for_resource_loaded() on something that isn't being loaded, thus hanging. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-21platforms/astbmc/witherspoon.c: Add NPU2 slot mappingsAlistair Popple1-0/+272
For NVLink2 to function PCIe devices need to be associated with the right NVLinks. This association is supposed to be passed down to Skiboot via HDAT but those fields are still not correctly filled out. To work around this we add slot tables for the NVLinks similar to what we have for P8+. Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-21platforms/astbmc/slots.c: Allow comparison of bus numbers when matching slotsAlistair Popple1-1/+1
When matching devices on multiple down stream PLX busses we need to compare more than just the device-id of the PCIe BDFN, so increase the mask to do so. Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-21hw/npu2.c: Fix device aperture calculationAlistair Popple1-2/+4
The POWER9 NPU2 implements an address compression scheme to compress 56-bit P9 physical addresses to 47-bit GPU addresses. System software needs to know both addresses, unfortunately the calculation of the compressed address was incorrect. Fix it here. Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-21libflash/libffs: Correctly update the actual size of the partitionCyril Bur1-1/+1
libffs has been updating FFS partition information in the wrong place which leads to incomplete erases and corruption. Fixes: 602dee45 libflash/libffs: Rework libffs Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-21Update default TSCR for P9Michael Neuling1-0/+3
Update default TSCR value for P9 as recommended by HW folk. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-21xive: Fix initialisation of xive_cpu_state structAndrew Donnellan1-0/+1
When using XIVE emulation with DEBUG=1, we run into crashes in log_add() due to the xive_cpu_state->log_pos being uninitialised (and thus, with DEBUG enabled, initialised to the poison value of 0x99999999). Zero out the xive_cpu_state to fix this. Fixes: 6480d9656348 ("XIVE: Base XIVE support for OPAL XICS emulation calls") Reported-by: Alastair D'Silva <alastair@d-silva.org> Suggested-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-21FSP: Add check to detect FSP R/R inside fsp_sync_msg()Vasant Hegde1-2/+11
OPAL sends MBOX message to FSP and updates message state from fsp_msg_queued -> fsp_msg_sent. fsp_sync_msg() queues message and waits until we get response from FSP. During FSP R/R we move outstanding MBOX messages from msgq to rr_queue including inflight message (fsp_reset_cmdclass()). But we are not resetting inflight message state. In extreme croner case where we sent message to FSP via fsp_sync_msg() path and FSP R/R happens before getting respose from FSP, then we will endup waiting in fsp_sync_msg() until everything becomes normal. This patch adds fsp_in_rr() check to fsp_sync_msg() and return error to caller if FSP is in R/R. CC: Ananth N Mavinakayanahalli <ananth@linux.vnet.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Acked-by: Ananth N Mavinakayanahalli <ananth@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-21phb4: Harden init with bad PHBsMichael Neuling1-0/+8
Currently if we read all 1's from the EEH or IRQ capabilities, we end up train wrecking on some other random code (eg. an assert() in xive). This hardens the PHB4 code to look for these bad reads and more gracefully fails the init for that PHB alone. This allows the rest of the system to boot and ignore those bad PHBs. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-20hw/npu2.c: Change MCD BAR allocation orderAlistair Popple1-2/+7
MCD BARs need to be correctly aligned to the size of the region. As GPU memory is allocated from the top of memory down we should start allocating from the highest GPU memory address to the lowest to ensure correct alignment. Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-20boot-tests: add OpenBMC supportStewart Smith2-2/+125
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-20NPU2: Add flag to nvlink config space indicating DL reset stateAlistair Popple4-5/+19
Device drivers need to be able to determine if the DL is out of reset or not so they can safely probe to see if links have already been trained. This patch adds a flag to the vendor specific config space indicating if the DL is out of reset. Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-20hw/npu2.c: Hardcode MSR_SF when setting up npu XTS contextsAlistair Popple1-2/+4
We don't support anything other than 64-bit mode for address translations so we can safely hardcode it. Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-20hw/npu2-hw-procedures.c: Add nvram option to override zcal calculationsAlistair Popple3-9/+30
In some rare cases the zcal state machine may fail and flag an error. According to hardware designers it is sometimes ok to ignore this failure and use nominal values for the calculations. In this case we add a nvram variable (nv_zcal_override) which will cause skiboot to ignore the failure and use the nominal value specified in nvram. Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-19test/hello_world: Properly report P9MAMBO pathMichael Ellerman1-1/+1
In the P9 hello script we look for $P9MAMBO_BINARY, but then if we don't find it we print a message using $MAMBO_BINARY, which is confusing: $ set -x P9MAMBO_BINARY run/p9/run_cmdline $ ./test/hello_world/run_mambo_p9_hello_world.sh Could not find executable P9MAMBO_BINARY (/opt/ibm/systemsim-p9//). Fix it so the right thing is printed: Could not find executable P9MAMBO_BINARY (/opt/ibm/systemsim-p9//run/p9/run_cmdline). Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-19capi: Handle HMI eventsChristophe Lombard6-83/+142
Find the CAPP on the chip associated with the HMI event for PHB4. The recovery mode (re-initialization of the capp, resume of functional operations) is only available with P9 DD2. A new patch will be provided to support this feature. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-19capi: Load capp microcodeChristophe Lombard8-200/+292
CAPP microcode flash download and CAPP upload for PHB4. A new file 'capp.c' is created to receive common capp code for PHB3 and PHB4. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-19capi: Enable capi mode for PHB4Christophe Lombard5-6/+422
Enable the Coherently attached processor interface. The PHB is used as a CAPI interface. CAPI Adapters can be connected to either PEC0 or PEC2. Single port CAPI adapter can be connected to either PEC0 or PEC2, but Dual-Port Adapter can be only connected to PEC2 CAPP0 attached to PHB0(PEC0 - single port) CAPP1 attached to PHB3(PEC2 - single or dual port) As we did for PHB3, a new specific file 'phb4-capp.h' is created to contain the CAPP register definitions. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-19capi: Move phb3 capp registers to specialized filesChristophe Lombard4-33/+54
The definitions of the CAPP registers for PHB3 are moved in a specific file. The updated file capp.h will be used for the common functionalities about the CAPP for PHB3 and PHB4. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-19capi: Externalize capp timebase synchronizationChristophe Lombard3-25/+27
Externalize the chiptod code. this code will be common for PHB3 and PHB4. The reference to the structure PHB3 is remove and new arguments appear due to specific address registers. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-19FSP/CONSOLE: Fix possible NULL dereferenceVasant Hegde1-2/+7
Fix coverity warning message. Null pointer dereferences (NULL_RETURNS) /hw/fsp/fsp-console.c: 295 in fsp_open_vserial() 289 290 fs->open = true; 291 292 fs->poke_msg = fsp_mkmsg(FSP_CMD_VSERIAL_OUT, 2, 293 msg->data.words[0], 294 msg->data.words[1] & 0xffff); >>> CID 145796: Null pointer dereferences (NULL_RETURNS) >>> Dereferencing a null pointer "fs->poke_msg". 295 fs->poke_msg->user_data = fs; 296 297 fs->in_buf->partition_id = fs->out_buf->partition_id = part_id; 298 fs->in_buf->session_id = fs->out_buf->session_id = sess_id; 299 fs->in_buf->hmc_id = fs->out_buf->hmc_id = hmc_indx; 300 fs->in_buf->data_offset = fs->out_buf->data_offset = Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-19mambo: Update P9 PVR to reflect Scale out 24 core chipsMichael Neuling1-2/+2
The P9 PVR bits 48:51 don't indicate a revision but instead different configurations. From BookIV we have: Bits: Configuration 0: Scale out 12 cores 1: Scale out 24 cores 2: Scale up 12 cores 3: Scale up 24 cores Skiboot will mostly the use "Scale out 24 core" configuration (ie. SMT4 not SMT8) so reflect this in mambo. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-19Ensure P9 DD1 workarounds apply only to NimbusMichael Neuling4-27/+41
The workarounds for P9 DD1 are only needed for Nimbus. P9 Cumulus will be DD1 but don't need these same workarounds. This patch ensures the P9 DD1 workarounds only apply to Nimbus. It also renames some things to make clear what's what. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-19hdata_to_dt: Add PVR overrides to the usage textOliver O'Halloran1-1/+8
Save us a few headaches in the future. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-19ipmi-sel: Fix missing typo, line length and correct eSEL stylisationAndrew Jeffery1-1/+1
It might seem impossible to some that missing typos can be fixed without being first added, but here we are. Further, reduce the line length to sensible limits to ensure Joel provides a Reviewed-by, and fix eSEL stylisation to hopefully extract similar tags from the rest of the peanut gallery. Suggested-by: Joel Stanley <joel@jms.id.au> Suggested-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-19platforms/astbmc: Don't validate model on palmettoGavin Shan1-9/+2
The platform isn't compatible with palmetto until the root device-tree node's "model" property is NULL or "palmetto". However, we could have "TN71-BP012" for the property on palmetto. linux# cat /proc/device-tree/model TN71-BP012 This skips the validation on root device-tree node's "model" property on palmetto, meaning we check the "compatible" property only. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-19hw/phb4: Rework phb4_get_presence_state()Gavin Shan1-21/+11
There are two issues in current implementation: It should return errcode visibile to Linux, which has prefix OPAL_*. The code isn't very obvious. This returns OPAL_HARDWARE when the PHB is broken. Otherwise, OPAL_SUCCESS is always returned. In the mean while, It refactors the code to make it obvious: OPAL_PCI_SLOT_PRESENT is returned when the presence signal (low active) or PCIe link is active. Otherwise, OPAL_PCI_SLOT_EMPTY is returned. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-16hw/phys_map: Use GCIDs as a chip indexOliver O'Halloran8-30/+27
Currently we pass in a proc_chip structure to phys_map_get(). All we we really need from this structure is the Global Chip ID (GCID). This patch reworks the function so that we only need to pass the GCID which allows us to use it before the proc_chip structures have been initialised (i.e in the HDAT parser). Cc: Michael Neuling <mikey@neuling.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Acked-By: Michael Neuling <mikey@neuling.org> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-16hdata: Use GCID in LPC setupOliver O'Halloran1-2/+7
The HDAT has a notion of "chip ID" which is an arbitrary numbering of chips. This numbering isn't useful outside of the HDAT so we refer to chips uing their Global Chip ID (GCID). Currently we're using the HDAT chip ID in a few places and this patch fixes them. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-16core/pci: Use PCI slot's power facality in pci_enable_bridge()Gavin Shan3-160/+247
The current implmentation has incorrect assumptions: there is always a PCI slot associated with root port and PCIe switch downstream port and all of them are capable to change its power state by register PCICAP_EXP_SLOTCTL. Firstly, there might not a PCI slot associated with the root port or PCIe switch downstream port. Secondly, the power isn't controlled by standard config register (PCICAP_EXP_SLOTCTL). There are I2C slave devices used to control the power states on Tuleta. In order to use the PCI slot's methods to manage the power states, this does: * Introduce PCI_SLOT_FLAG_ENFORCE, indicates the request operation is enforced to be applied. * pci_enable_bridge() is split into 3 functions: pci_bridge_power_on() to power it on; pci_enable_bridge() as a place holder and pci_bridge_wait_link() to wait the downstream link to come up. * In pci_bridge_power_on(), the PCI slot's specific power management methods are used if there is a PCI slot associated with the PCIe switch downstream port or root port. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-16platforms/ibm-fsp/firenze: Refactor firenze_pci_setup_power_mgt()Gavin Shan1-35/+44
This refactors firenze_pci_setup_power_mgt() and no logicial changes introduced: * Avoid nested if block; * Remove the local variable @buddy. The information is retrieved directly from struct firenze_pci_slot_info::buddy; * Comments to explain the fixed register offset (0x69) for slot's power control and shared power state between local slot and its buddy. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-16platforms/ibm-fsp/firenze: PCI slot fixup improvementGavin Shan1-46/+53
This introduces another data struct to describe the PCI slot fixup information. With that, the PCI slot fixup information table is decoupled from the PCI slot information table, to make the code easier to be maintained. In the meanwhile, the PCI slot information struct, which has been complexed, is simplified. It shouldn't introduce any functional changes. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-16platforms/ibm-fsp/firenze: Fix PCI slot power-off patternGavin Shan1-2/+2
When powering off the PCI slot, the corresponding bits should be set to 0bxx00xx00 instead of 0bxx11xx11. Otherwise, the specified PCI slot can't be put into power-off state. Fortunately, it didn't introduce any side-effects so far. Cc: stable # 5.3.0+ Fixes: 6884fe63ba1e ("platforms/ibm-fsp: Support PCI slot") Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-15core/pci: Make the conditions for device type quirk obviousGavin Shan1-3/+2
The device type should be fixed to downstream port when it seats behinds behind a upstream port, which is connected to root port directly and its VDID is 0x874810b5. This reorders the conditions to make it a bit obvious: parent, parent's device type, device's VDID and device type in sequence. No logicial changes. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-15core/pci: Use macro as vendor ID register offsetGavin Shan1-4/+4
This uses macro as PCI config register (vendor ID) offset because it's more indicative. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-15hw/phb3: Use cached vendor/device IDs in phb3_check_device_quirks()Gavin Shan1-19/+20
This uses the cached vendor/device IDs in phb3_check_device_quirks(). Also, to give the code and comment a cleaup. No logical changes are introduced. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-15core/pci: Use cached vendor/device IDs in quirksGavin Shan4-11/+7
The PCI device vendor/device IDs have been cached to pd->vdid, no need to pass them in pci_handle_quirk(). This also introduces two macros to extract vendor/device fields and they are useful afterwards. No logical changes introduced. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-15hw/ipmi/ipmi-sel: missing newline in prlog warningStewart Smith1-1/+1
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-15occ: Set return variable to correct valueCyril Bur1-0/+1
When entering this section of code rc will be zero. If fsp_mkmsg() fails the code responsible for printing an error message won't be set. Resetting rc should allow for the error case to trigger if fsp_mkmsg fails. Fixes: 3c64f79ad2220d03a0af49d44f0548e08da54a44 Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com> [stewart@linux.vnet.ibm.com: add Fixes] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-15core/fdt: Always add a reserve mapOliver O'Halloran1-0/+3
Currently we skip adding the reserved ranges block to the generated FDT blob if we are excluding the root node. This can result in a DTB that dtc will barf on because the reserved memory ranges overlap with the start of the dt_struct block. As an example: $ fdtdump broken.dtb -d /dts-v1/; // magic: 0xd00dfeed // totalsize: 0x7f3 (2035) // off_dt_struct: 0x30 <----\ // off_dt_strings: 0x7b8 | this is bad! // off_mem_rsvmap: 0x30 <----/ // version: 17 // last_comp_version: 16 // boot_cpuid_phys: 0x0 // size_dt_strings: 0x3b // size_dt_struct: 0x788 /memreserve/ 0x100000000 0x300000004; /memreserve/ 0x3300000001 0x169626d2c; /memreserve/ 0x706369652d736c6f 0x7473000000000003; *continues* With this patch: $ fdtdump working.dtb -d /dts-v1/; // magic: 0xd00dfeed // totalsize: 0x803 (2051) // off_dt_struct: 0x40 // off_dt_strings: 0x7c8 // off_mem_rsvmap: 0x30 // version: 17 // last_comp_version: 16 // boot_cpuid_phys: 0x0 // size_dt_strings: 0x3b // size_dt_struct: 0x788 // 0040: tag: 0x00000001 (FDT_BEGIN_NODE) / { // 0048: tag: 0x00000003 (FDT_PROP) // 07fb: string: phandle // 0054: value phandle = <0x00000001>; *continues* Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
generated by cgit v1.1 at 2024-07-10 00:04:59 +0000