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2017-07-13phb4: Verbose EEH optionsBenjamin Herrenschmidt1-24/+118
Enabled via nvram pci-eeh-verbose=true. ie. nvram -p ibm,skiboot --update-config pci-eeh-verbose=true Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-13phb4: Print more info when PHB fencesBenjamin Herrenschmidt1-7/+37
For now at PHBERR level. We don't have room in the diags data passed to Linux for these unfortunately. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-13lpc: remove double LPC prefix from messagesJoel Stanley1-20/+20
The file has pr_fmt set so messages come out like this: [ 73.382366442,7] LPC: LPC: Routing irq 9, policy: 0 (r=1) [ 73.382369213,7] LPC: LPC: SerIRQ 9 using route 0 targetted at OPAL Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-12opal-ci/fetch-debian-jessie-installer: follow redirectsStewart Smith1-2/+2
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-12test/qemu-jessie: bail out fast on kernel panicStewart Smith1-0/+1
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-12test/qemu-jessie: dump boot log on failureStewart Smith1-0/+1
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-12travis: add fedora26Stewart Smith2-0/+8
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-12xz: add fallthrough annotations to silence GCC7 warningStewart Smith2-8/+8
The fallthrough is intentional (or at least appears to be), and I'd rather not have warnings show up in the skiboot build at all. Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-12xive: Enable memory backing of queuesBenjamin Herrenschmidt2-6/+41
This dedicates 6x64k pages of memory permanently for the XIVE to use for internal queue overflow. This allows the XIVE to deal with some corner cases where the internal queues might prove insufficient. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-12xive: Properly get rid of donated indirect pages during resetBenjamin Herrenschmidt2-38/+105
Otherwise they keep being used accross kexec causing memory corruption in subsequent kernels once KVM has been used. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-12cpu: Better handle unknown flags in opal_reinit_cpus()Benjamin Herrenschmidt1-3/+3
At the moment, if we get passed flags we don't know about, we return OPAL_UNSUPPORTED but we still perform whatever actions was requied by the flags we do support. Additionally, on P8, we attempt a SLW re-init which hasn't been supported since Murano DD2.0 and will crash your system. It's too late to fix on existing systems so Linux will have to be careful at least on P8, but to avoid future issues let's clean that up, make sure we only use slw_reinit() when HILE isn't supported. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [stewart@linux.vnet.ibm.com: retain OPAL_UNSUPPORTED] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-11cpu: Unconditionally cleanup TLBs on P9 in opal_reinit_cpus()Benjamin Herrenschmidt1-2/+11
This can work around problems where Linux fails to properly cleanup part or all of the TLB on kexec. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-07Fix scom addresses for power9 nx checkstop hmi handling.Mahesh Salgaonkar1-7/+20
Scom addresses for NX status, DMA & ENGINE FIR and PBI FIR has changed for Power9. Fixup thoes while handling nx checkstop for Power9. Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-07Fix scom addresses for power9 core checkstop hmi handling.Mahesh Salgaonkar1-5/+56
Scom addresses for CORE FIR (Fault Isolation Register) and Malfunction Alert Register has changed for Power9. Fixup those while handling core checkstop for Power9. Without this change HMI handler fails to check for correct reason for core checkstop on Power9. Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-04core/mem_region: check return value of add_regionStewart Smith1-2/+5
The only sensible thing to do if this fails is to abort() as we've likely just failed reserving reserved memory regions, and nothing good comes from that. Found by static analysis Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-04hw/occ: remove dead codeStewart Smith1-5/+2
ulta_turbo_supported will always be true in this codepath, so the condition isn't needed found by static analysis Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-04hw/occ: explicitly document fallthroughStewart Smith1-0/+1
Found by static analysis Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-04doc/device-tree: improve root node docStewart Smith1-20/+29
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-04hdata/vpd: Don't dereference possible NULL model_nameStewart Smith1-4/+4
It's legitimate to just add model-name to the device tree if we have one, which is what the hdata logic tries to do, but subtley fails in one of the code paths. Found by static analysis Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-04hw/fsi-master: check zalloc return valueStewart Smith1-1/+2
If we can't allocate enough memory for each chip struct mfsi, we're not going to go so well during boot, so just assert that we allocated the memory. Found by static analysis Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-03skiboot-5.7-rc1 release notesv5.7-rc1Stewart Smith1-0/+979
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-30cpu: Cleanup AMR and IAMR when re-initializing CPUsBenjamin Herrenschmidt2-0/+31
There's a bug in current Linux kernels leaving crap in those registers accross kexec and not sanitizing them on boot. This breaks kexec under some circumstances (such as booting a hash kernel from a radix one on P9 DD2.0). The long term fix is in Linux, but this workaround is a reasonable way of "sanitizing" those SPRs when Linux calls opal_reinit_cpus() and shouldn't have adverse effects. We could also use that same mechanism to cleanup other things as well such as restoring some other SPRs to their default value in the future. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-30Set POWER9 RPR SPRMichael Neuling1-0/+3
Set POWER9 RPR SPR to 0x00000103070F1F3F. Same value as P8. Without this, thread priorities inside a core don't work. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-30phb4: Fix number of index bits in IODA tablesBenjamin Herrenschmidt1-1/+1
On PHB4 the number of index bits in the IODA table address register was bumped to 10 bits to accomodate for 1024 MSIs and 1024 TVEs (DD2). However our macro only defined the field to be 9 bits, thus causing "interesting" behaviours on some systems. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-30npu2: Use phys-map to get MMIO BARsAndrew Donnellan2-50/+50
Commit bdea201a4c4b ("hw/npu2.c: Use phys-map to get GPU memory BARs") added use of phys-map for setting GPU memory BARs. Move the MMIO BARs over to using phys-map as well. Acked-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-27skiboot: Handle combined units node in the imc dtMadhavan Srinivasan2-0/+66
Add code to detect combined unit nodes in the imc device tree. Due to HW/OCC restriction mcs* units are paired and monitored by the nest microcode. Microcode today does not support monitoring of individual mcs* unit events, so the patch first remove these mcs* from the imc device tree if found. Secondly to enable or disbale combined units nodes like "mcs01", "mcs23","mcs45" and "mcs67", additional parser loop is added to disable_unavailable_units(). Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-27skiboot: Add documentation for IMC opal callAnju T Sudhakar1-0/+87
Add documentation for new OPAL Call APIs added for In Memory Collection(IMC) infrastructure. Three new OPAL Call APIs are added and they are opal_imc_counters_init(int Domain, u64 address, u64 cpu_pir) opal_imc_counters_start(int Domain, u64 cpu_pir) opal_imc_counters_stop(int Domain, u64 cpu_pir) Document details the input parameters and return values. Acked-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Anju T Sudhakar <anju@linux.vnet.ibm.com> Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-27skiboot: Add opal calls to init/start/stop IMC devicesAnju T Sudhakar3-1/+213
Add new opal calls to init, start and stop the IMC nest/core units. To initialize the core IMC counters, it takes a physical address per core as an input and writes that address to PDBAR[14:50] bits. It initializes the htm_mode and event_mask, where it selects the time interval at which the counter values must be posted to the given memory location and enables the counters to start running by setting the appropriate bits. To disable/enable the nest IMC counters (stop or resume counting), writes into "command" field of the nest control block in the reserve memory location. To disable/enable the core IMC counters (stop or resume counting), writes into appropriate bits of htm_mode to disable the counters. Acked-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Hemant Kumar <hemant@linux.vnet.ibm.com> Signed-off-by: Anju T Sudhakar <anju@linux.vnet.ibm.com> Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> [stewart@linux.vnet.ibm.com: use pr_fmt rather than hardcode IMC prefix] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-27skiboot: Find the IMC DTBMadhavan Srinivasan7-1/+464
IMC (In Memory Collection) catalog is a repository of information about the Performance Monitoring Units (PMUs) and their events under the IMC infrastructure. The information include : - The PMU names - Event names - Event description - Event offsets - Event scale - Event unit The catalog is provided as a flattened device tree (dtb). Processors with different PVR values may have different PMU or event names. Hence, for each processor, there can be multiple device tree binaries (dtbs) containing the IMC information. Each of the dtb is compressed and forms a sub-partition inside the PNOR partition "IMA_CATALOG". Here is a link to the commit adding this partition to PNOR : https://github.com/open-power/pnor/commit/c940142c6dc64dd176096dc648f433c889919e84 So, each compressed dtb forms a sub-partition inside the IMC pnor partition and can be accessed/loaded through a sub-partition id which is nothing but the PVR id. Based on the current processor's PVR, the appropriate sub-partion will be loaded. Note however, that the catalog information is in the form of a dtb and the dtb is compressed too. So, the sub-partition loaded must be decompressed first before we can actually use it. It is important to mention here that while a PNOR image built for one processor is specific to only that processor and isn't portable, a single system generation (Processor version) may have multiple revisions and these revisions may have some changes in their IMC PMUs and events, and hence, the need for multiple IMC DTBs. The sub-partition that we obtain from the IMC pnor partition is a compressed device tree binary. We uncompress it using the libxz's functions. After uncompressing it, we link the device tree binary to the system's device tree. The kernel can now access the device tree and get the IMC PMUs and their events' information. Not all the IMC PMUs listed in the device tree may be available. This is indicated by imc availability vector (which is a part of the IMC control block structure). We need to check this vector and make sure to remove the IMC device nodes which are unavailable. Signed-off-by: Hemant Kumar <hemant@linux.vnet.ibm.com> Signed-off-by: Anju T Sudhakar <anju@linux.vnet.ibm.com> Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> [stewart@linux.vnet.ibm.com: use pr_fmt, fix failure path for resource load] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-27skiboot: Add a library for xzHemant Kumar10-2/+2937
This patch adds a library for compression/decompression using xz. The code comes from http://tukaani.org/xz/embedded.html. The codebase has been kept as-is with a new Makefile.inc. For libxz/Makefile.inc and Makefile.main : Signed-off-by: Hemant Kumar <hemant@linux.vnet.ibm.com> Acked-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Hemant Kumar <hemant@linux.vnet.ibm.com> Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-27skiboot: Nest IMC macro definitionsHemant Kumar1-0/+119
Add the macros needed for Nest IMC (In Memory Collection) instrumentation support by creating a new file in include/ called "imc.h". Also, add a header "nest_imc.h" containing an array of possible list of nest PMUs. These macros are needed to discover the catalog subpartition, enable and disable the nest IMC instrumentation. Acked-by: Michael Neuling <mikey@neuling.org> Reviewed-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Hemant Kumar <hemant@linux.vnet.ibm.com> [Anju: changed NEST_IMC_RESUME to NEST_IMC_RUNNING] Signed-off-by: Anju T Sudhakar <anju@linux.vnet.ibm.com> [maddy: Removed nest_imc.h and updated few macros] Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-27dt: Add phandle fixup helpersMadhavan Srinivasan3-2/+75
When there is a new device tree that needs to be added to the main dt of the opal (ex, IMC catalog dtb loaded from pnor partition), we need to check for the phandle values in the new incoming device tree before attaching it. Reason is that, incoming device tree could already have phandle values initialized for its nodes. Now, if we attach this new device tree to the main opal DT, we could potentially hit phandle duplicate error (since the phandles value usually start with 1). To avoid this, a new helper function dt_adjust_subtree_phandle() is added to scan the incoming device tree and update node "phandle" accordingly based on the opal "last_phandle" value. Add to this, helper function also supports updates of "properties" with in a node which may refer the "phandle" value in the incoming device tree. Helper function will also fix the "properties" field accordingly. Acked-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-27dt: Add helper function for last_phandle updatesMadhavan Srinivasan3-6/+22
Add helper functions for "last_phandle" access/update and modify functions to use helper functions. Acked-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-27skiboot/doc: Add devicetree binding document for IMCMadhavan Srinivasan1-0/+72
Add a device tree binding documentation for the In Memory Collection counter infrastructure. Acked-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-27skiboot/doc: Add doc/imc.rst documentationMadhavan Srinivasan2-0/+55
Add imc.rst documentation to detail the In-Memory Collection Counters infrastructure and interface Acked-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-26libflash/libffs: Zero checksum wordsCyril Bur1-0/+16
On writing ffs entries to flash libffs doesn't zero checksum words before calculating the checksum across the entire structure. This causes an inaccurate calculation of the checksum as it may calculate a checksum on non-zero checksum bytes. This patch solves this by zeroing the entire structure which is to be written to the flash before calculating the checksum across the struct. Fixes: 602dee45 libflash/libffs: Rework libffs Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-26cpu: Support setting HID[RADIX] and set it by default on P9Benjamin Herrenschmidt5-0/+52
This adds new opal_reinit_cpus() flags to setup radix or hash mode in HID[8] on POWER9. By default HID[8] will be set. On P9 DD1.0, Linux will change it as needed. On P9 DD2.0 hash works in radix mode (radix is really "dual" mode) so KVM won't break and existing kernels will work. Newer kernels built for hash will call this to clear the HID bit and thus get the full size of the TLB as an optimization. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-26cpu: Rework HILE changeBenjamin Herrenschmidt3-31/+48
Create a more generic helper for changing HID0 bits on all processors. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-26cpu: Make init_hid() local to cpu.cBenjamin Herrenschmidt3-4/+3
No point doing that from init on the main CPU while it's done already inside cpu.c for secondaries. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-26Add "cleanup_global_tlb" for P9 and laterBenjamin Herrenschmidt2-0/+61
Uses broadcast TLBIE's to cleanup the TLB on all cores and on the nest MMU By default this works with older binutils but there is a version (in #defines) that requires newer binutils and which documents what the instructions are. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-26Rename cleanup_tlb() to cleanup_local_tlb()Benjamin Herrenschmidt3-4/+4
It uses tlbiel and only cleans up the TLB of the calling core Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-26Move cleanup_tlb from head.S to misc.SBenjamin Herrenschmidt2-13/+13
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-26Big log level reduction...Benjamin Herrenschmidt15-51/+46
90% of what we print isn't useful to a normal user. This dramatically reduces the amount of messages printed by OPAL in normal circumstances. We still need to add a way to bump the log level at boot based on a BMC scratch register or some HDAT property. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-26init: Silence messages and call ourselves "OPAL"Benjamin Herrenschmidt1-2/+2
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-26flash: Silence some messagesBenjamin Herrenschmidt1-2/+6
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-26cpu: Add a space to #threads messageBenjamin Herrenschmidt1-3/+3
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-26libffs: Fix ffs_lookup_part() return valueBenjamin Herrenschmidt1-4/+6
It would return success when the part wasn't found Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-26xive: Remove historical BAR reading codeBenjamin Herrenschmidt1-80/+11
We always use physmap to assign them, take out the code that tries to read and check the validity of the setup done by HB or cronus. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-26psi: Switch to ESB mode laterBenjamin Herrenschmidt1-4/+4
There's an errata, if we switch to ESB mode before setting up the various ESB mode related registers, a pending interrupts can go wrong. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-26lpc: Enable "new" SerIRQ modeBenjamin Herrenschmidt1-1/+9
So we don't have to clear the bits on EOI manually. This works in conjunction with the DD2 test in psi.c Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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