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2017-09-19hdata: Add wafer-location propertyVasant Hegde1-0/+4
Extract wafer-location from ECID and add property under xscom node. bits 64:71 are the chip x location (7:0) bits 72:79 are the chip y location (7:0) Sample output: ------------- [root@wsp xscom@623fc00000000]# lsprop ecid ecid 019a00d4 03100718 852c0000 00fd7911 [root@wsp xscom@623fc00000000]# lsprop wafer-location wafer-location 00000085 0000002c Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-19hdata: Add wafer-id propertyVasant Hegde1-0/+25
Wafer id is derived from ECID data. bits 4:63 are the wafer id ( ten 6 bit fields each containing a code) Sample output: ------------- [root@wsp xscom@623fc00000000]# lsprop ecid ecid 019a00d4 03100718 852c0000 00fd7911 [root@wsp xscom@623fc00000000]# lsprop wafer-id wafer-id "6Q0DG340SO" Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-19hdata: Add ecid propertyVasant Hegde2-1/+28
Add ecid property under xscom node. Sample output: ------------- [root@wsp xscom@623fc00000000]# lsprop ecid ecid 019a00d4 03100718 852c0000 00fd7911 Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-19Add Documenation for opal_slw_set_regAkshay Adiga1-0/+46
Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Reviewed-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-19SLW: Removing timebase related flags for stop4Akshay Adiga1-2/+2
When a core enters stop4, it does not loose decrementer and time base. Hence removing flags OPAL_PM_DEC_STOP and OPAL_PM_TIMEBASE_STOP. Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Reviewed-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-19SLW: Allow deep states if homer address is knownAkshay Adiga1-6/+17
Use a common variable has_wakeup_engine instead of has_slw to tell if the a) SLW image is populated in case of power8 b) CME image is populated in case of power9 Currently we expect CME to be loaded if homer address is known ( except for simulators) Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Reviewed-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-19SLW: Configure self-restore for HRMORAkshay Adiga1-0/+29
Make a stop api call using libpore to restore HRMOR register. HRMOR needs to be cleared so that when thread exits stop, they arrives at linux system_reset vector (0x100). Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Reviewed-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-19SLW: Add opal_slw_set_reg support for power9Akshay Adiga1-20/+40
This OPAL call is made from Linux to OPAL to configure values in various SPRs after wakeup from a deep idle state. Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Reviewed-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-19Revert "hw/slw.c: Offline code still uses p8 bits"Stewart Smith1-3/+0
This reverts commit 0a2710381f34e6b4c03cff1fa76bc1b74f280ecd. Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-19libpore: Build fix for p9_stop_apiAkshay Adiga2-2/+3
Build fix for "declaration-after-statement". Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Reviewed-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-19Add glibc style endianess check in CCANAkshay Adiga1-0/+9
CCAN adds support for glibc style in the following commit : https://github.com/rustyrussell/ccan/commit/759ac0f0564104d5028acd47c3e9fdb858c96d1d Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Reviewed-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-19SLW: Add support for p9_stop_apiAkshay Adiga10-1/+2585
p9_stop_api's are used to set SPR state on a core wakeup form a deeper low power state. p9_stop_api uses low level platform formware and self-restore microcode to restore the sprs to requested values. Code is taken from : https://github.com/open-power/hostboot/tree/master/src/import/chips/p9/procedures/utils/stopreg Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Reviewed-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-19core/flash: Only expect ELF header for BOOTKERNEL partition flash resourceSuraj Jitindar Singh1-9/+23
When loading a flash resource which isn't signed (secure and trusted boot) and which doesn't have a subpartition, we assume it's the BOOTKERNEL since previously this was the only such resource. Thus we also assumed it had an ELF header which we parsed to get the size of the partition rather than trusting the actual_size field in the FFS header. A previous commit (9727fe3 DT: Add ibm,firmware-versions node) added the version resource which isn't signed and also doesn't have a subpartition, thus we expect it to have an ELF header. It doesn't so we print the error message "FLASH: Invalid ELF header part VERSION". It is a fluke that this works currently since we load the secure boot header unconditionally and this happen to be the same size as the version partition. We also don't update the return code on error so happen to return OPAL_SUCCESS. To make this explicitly correct; only check for an ELF header if we are loading the BOOTKERNEL resource, otherwise use the partition size from the FFS header. Also set the return code on error so we don't erroneously return OPAL_SUCCESS. Add a check that the resource will fit in the supplied buffer to prevent buffer overrun. Fixes: 9727fe3 (DT: Add ibm,firmware-versions node) Reported-by: Pridhiviraj Paidipeddi <ppaidipe@linux.vnet.ibm.com> Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-19doc: Update OPAL API call IDs for OPAL_NPU_Stewart Smith1-3/+3
Documentation was always the one that was wrong, so we update it to reflect what was merged. Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-19doc: Add _build directory to .gitignoreBenjamin Herrenschmidt1-0/+1
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-19PHB4: Default to PCIe GEN3 on POWER9 DD2.00Stewart Smith1-0/+6
You can use the NVRAM override for DD2.00 screened parts. Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-19skiboot-5.4.7 release notesStewart Smith1-0/+30
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> (cherry picked from commit 17661bef0e0968e60e0938e646e6d3ab0e201d46) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-19add skiboot-5.1.21 release notesStewart Smith1-0/+24
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> (cherry picked from commit 7d64a8b4daa00a78e49493668ad4fd6789bfc883) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-18hdat: fix parsing of P8 hdatStewart Smith2-6/+3
Also fixes hdat_to_dt test cases. Fixes: ad484081ef8a51811e7902aec436fa8f1ca9604a Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-15npu2: hw-procedures: Add settings to PHY_RESETReza Arbab1-0/+10
Set a few new values in the PHY_RESET procedure, as specified by our updated programming guide documentation. Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-15hdata: Parse extra NVLink infoOliver O'Halloran2-1/+32
Add parsing for the link speed information and the OCC GPU presence flags. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-15hdata: Parse NVLink informationOliver O'Halloran4-2/+202
Add the per-chip structures that descibe how the A-Bus/NVLink/OpenCAPI phy is configured. This generates the npu@xyz nodes for each chip on systems that support it. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-15hdata: Parse IOSLOT informationOliver O'Halloran2-0/+470
Add structure definitions that describe the physical PCIe topology of a system and parse them into the device-tree based PCIe slot description. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-15hdata: Add xscom_to_pcrd()Oliver O'Halloran1-0/+39
Iterating the SPPCRD structures (per chip data) is a fairly common operation in the HDAT parser. Iterating the tuples directly is somewhat irritating since we need to check for disabled chips, etc on every pass. A better way to handle this is to iterate throught he xscom nodes (generated from the SPPCRD data) and map from the xscom node to the originating structure. This patch adds a function to do that. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-15hdata: Add an idata array iteratorOliver O'Halloran2-0/+87
Adds HDIF_get_iarray() which retrieves and validates an internal array header and HDIF_iarray_for_each() for walking the individual array entries. This reduces the amount of get-then-check boilerplate that we have with the existing HDIF_get_iarray_item() method for iterating internal data arrays. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-15libc: add strnlen()Oliver O'Halloran2-0/+14
Sometimes handy. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-15core: make is_rodata test-friendlyOliver O'Halloran1-3/+10
Add a dummy is_rodata() implementation for use inside test code. Currently we don't need to make this actually check if the given pointer is actually read-only, but someone might want it to work properly in the future. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-15convert new witherspoon to dt helperOliver O'Halloran1-1/+1
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-15witherspoon: Deprecate manual npu creationOliver O'Halloran1-4/+54
In the future we will always create the npu nodes based on what's in the HDAT. For now we seperate witherspoon into an old and new platform where the old platform will assume a sequoia planar and create the relevant NPU nodes for that planar. If you have a redbud system this will be broken, but this should be fine for most cases. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-15platform/witherspoon: Add slot names to tableOliver O'Halloran2-22/+68
Add the other PCIe devices to the witherspoon slot tables. This provides a fall back for systems without IOSLOT information in the HDAT. This is mainly to allow DD1 systems to continue being useful. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-15astbmc: Add methods for handing DT based slotsOliver O'Halloran2-0/+49
Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-15core/pci-slots: Move slot-label construction to a helperOliver O'Halloran3-32/+35
Move this out of the astbmc specific part into a generic helper. This allows us to use it more commonly. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-15core/pcie-slots: Make dynamic slot creation genericOliver O'Halloran3-62/+66
astbmc has some code to handle devices that are behind a "slot" on a riser card that can't be added to the static slot tables for a system. We probably want to use this code outside the slot table handling so move it somewhere generic and rework it so slot table specifics aren't buried inside it. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-15core/pci-dt-slot: Represent PCIe slots in the devicetreeOliver O'Halloran3-0/+238
In P9 we get information about the physical PCIe slot topology through the HDAT. As a rule we never directly consume the HDAT inside of Skiboot and we always parse and incorporate the data from HDAT into the Skiboot device tree. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> [stewart@linux.vnet.ibm.com: add (C) header] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-15hw/slw.c: Offline code still uses p8 bitsBalbir Singh1-0/+3
I'm seeing an infinite loop while hot unplugging a CPU. This is a workaround till we do the right things for p9. May be a candidate for backporting The messages I see in an infinite loop are: [ 740.250192896,3] LIBPORE: Core ID = 20 is not within valid range of [0;15] [ 740.250230176,3] SLW: Failed to set spr for CPU 51 When trying to hotunplug core id 20. For now the patch just skips calling p8_pore* on p9 machines. Signed-off-by: Balbir Singh <bsingharora@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-15pflash: Fix erase command for unaligned start addressSuraj Jitindar Singh1-1/+1
The erase_range() function handles erasing the flash for a given start address and length, and can handle an unaligned start address and length. However in the unaligned start address case we are incorrectly calculating the remaining size which can lead to incomplete erases. If we're going to update the remaining size based on what the start address was then we probably want to do that before we overide the origin start address. So rearrange the code so that this is indeed the case. Reported-by: Pridhiviraj Paidipeddi <ppaidipe@in.ibm.com> Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Reviewed-by: Cyril Bur <cyril.bur@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-15phb4: Use link if degradedMichael Neuling1-1/+7
In the recent change: 3f936bae97 phb4: Retrain link if degraded We retrain if the link is degraded. We do 3 retries to get an optimal link. Unfortunately if the last retry fails, we mark the PHB as bad and don't use it. Hence that PHB is lost even though it actually trained (just degraded). This fixes the problem by printing an error message (as below) but still marking the PHB as good. [ 7.179320404,3] PHB#0005[0:5]: LINK: Link degraded [ 8.387346665,3] PHB#0005[0:5]: LINK: Link degraded [ 10.078409137,3] PHB#0005[0:5]: LINK: Link degraded [ 11.281477269,3] PHB#0005[0:5]: LINK: Link degraded [ 11.283123885,3] PHB#0005[0:5]: LINK: Degraded but no more retries Signed-off-by: Michael Neuling <mikey@neuling.org> Acked-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-12phb4: Retrain link if degradedMichael Neuling1-1/+133
On P9 Scale Out (Nimbus) DD2.0 and Scale in (Cumulus) DD1.0 (and below) the PCIe PHY can lockup causing training issues. This can cause a degradation in speed or width in ~5% of training cases (depending on the card). This is fixed in later chip revisions. This issue can also cause PCIe links to not train at all, but this case is already handled. This patch checks if the PCIe link has trained optimally and if not, does a full PHB reset (to fix the PHY lockup) and retrain. One complication is some devices are known to train degraded unless device specific configuration is performed. Because of this, we only retrain when the device is in a whitelist. All devices in the current whitelist have been testing on a P9DSU/Boston, ZZ and Witherspoon. We always gather information on the link and print it in the logs even if the card is not in the whitelist. For testing purposes, there's an nvram to retry all PCIe cards and all P9 chips when a degraded link is detected. The new option is 'pci-retry-all=true' which can be set using: nvram -p ibm,skiboot --update-config pci-retry-all=true This option may increase the boot time if used on a badly behaving card. Signed-off-by: Michael Neuling <mikey@neuling.org> [stewart@linux.vnet.ibm.com: fix Cumulus VERS_MAJ r.e. Mikey mail] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-12phb4: Make link retries a #defineMichael Neuling2-1/+2
Make link retries a #define rather than open coding it in the PHB4 init code. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-12pci: Make pci_wait_crs() globalMichael Neuling2-1/+2
We are going need pci_wait_crs() in the PHB4 code so make it global. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-12phb4: Split phb4_get_link_state() into a new functionMichael Neuling1-6/+21
Split phb4_get_link_state() into a new function so that it can be reused to get info on the speed and width of the link. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-12phb4: Move nvram read of pci-eeh-mmio initMichael Neuling1-1/+3
Move nvram read to the PHB4 init code so that's it's only read once, rather than every time we go though PHB reset. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-12phb4: Remove stable retriesMichael Neuling3-9/+0
This code was never used (since retries is set to 0), it's not very useful and it makes the code harder to read. So lets just remove it. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-12xive: Fix opal_xive_dump_tm() to access W2 properlyBenjamin Herrenschmidt1-1/+7
The HW only supported limited access sizes. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-12xive: Documentation updatesBenjamin Herrenschmidt1-23/+107
Correct the documentation in a couple of places to match the actual behaviour and improve bits and pieces of it Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-12npu2: Add vendor cap for IRQ testingSam Bobroff1-0/+28
Provide a way to test recoverable data link interrupts via a new vendor capability byte. Signed-off-by: Sam Bobroff <sam.bobroff@au1.ibm.com> Acked-By: Alistair Popple <alistair@popple.id.au> ====== v2 -> v3: ====== * Corrected name of NPU RING (no 2). [Andrew Donnellan] * Corrected spelling of device. [Andrew Donnellan] hw/npu2.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-12npu2: Enable recoverable data link (no-stall) interruptsSam Bobroff2-15/+131
Allow the NPU2 to trigger "recoverable data link" interrupts. Signed-off-by: Sam Bobroff <sam.bobroff@au1.ibm.com> Acked-By: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-12npu2: Update NPU to NPU2 in comments and messagesSam Bobroff1-13/+13
Signed-off-by: Sam Bobroff <sam.bobroff@au1.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Acked-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-12xive: Make opal_xive_allocate_irq() properly try all chipsBenjamin Herrenschmidt1-17/+37
When requested via OPAL_XIVE_ANY_CHIP, we need to try all chips. We first try the current one (on which the caller sits) and if that fails, we iterate all chips until the allocation succeeds. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-12xive: Fix initialization & cleanup of HW thread contextsBenjamin Herrenschmidt1-36/+38
Instead of trying to "pull" everything and clear VT (which didn't work and caused some FIRs to be set), instead just clear and then set the PTER thread enable bit. This has the side effect of completely resetting the corresponding thread context. This fixes the spurrious XIVE FIRs reported by PRD and fircheck Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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