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2018-02-06skiboot v5.10-rc1 release notesv5.10-rc1Stewart Smith2-0/+1562
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-01-30capi: Disable CAPP virtual machinesVaibhav Jain1-0/+1
When exercising more than one CAPI accelerators simultaneously in cache coherency mode, the verification team is seeing a deadlock. To fix this a workaround of disabling CAPP virtual machines is suggested. These 'virtual machines' let PSL queue multiple CAPP commands for servicing by CAPP there by increasing throughput. Below is the error scenario described by the h/w team: " With virtual machines enabled we had a deadlock scenario where with 2 or more CAPI's in a system you could get in a deadlock scenario due to cast-outs that are required break the deadlock (evict lines that another CAPI is requesting) get stuck in the virtual machine queue by a command ahead of it that is being retried by the same scenario in the other CAPI. " So this patch updates CAPP APC Master Powerbus control register during CAPP init to also set Bit(12) that disables CAPP virtual machines. This forces processing of CAPP commands from PSL one at a time and thereby preventing above mentioned deadlock scenario. Signed-off-by: Vaibhav Jain <vaibhav@linux.vnet.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-01-30capi: Perform capp recovery sequence only when PBCQ is idleVaibhav Jain1-3/+4
Presently during a CRESET the CAPP recovery sequence can be executed multiple times in case PBCQ on the PEC is still busy processing in/out bound inflight transactions. This patch updates phb4_creset() to perform capp-recovery sequence via do_capp_recovery_scoms() only when PBCQ General Status Register reports no pending transactions. Signed-off-by: Vaibhav Jain <vaibhav@linux.vnet.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Reviewed-by: Christophe Lombard clombard@linux.vnet.ibm.com Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-01-30hdata/vpd: Add vendor propertyVasant Hegde1-0/+5
ibm,vpd blob contains VN field. Use that to populate vendor property for various FRU's. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-01-30sensors: occ: Skip power sensors with zero sample valueShilpasri G Bhat1-0/+21
APSS is not avialable on platforms like Zaius, Romulus where OCC can only measure Vdd (core) and Vdn (nest) power from the AVSbus reading. So all the sensors for APSS channels will be populated with 0. Different component power sensors like system, memory which point to the APSS channels will also be 0. As per OCC team (Martha Broyles) zero'ed power sensor means that the system doesnot have it. So this patch filters out these sensors. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-01-30sensors: occ: Skip GPU sensors for non-gpu systemsShilpasri G Bhat1-0/+7
Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-01-30xive: Mask MMIO load/store to bad location FIRFrederic Barrat2-1/+9
For opencapi, the trigger page of an interrupt is mapped to user space. The intent is to write the page to raise an interrupt but there's nothing to prevent a user process from reading it, which has the infortunate consequence of checkstopping the system. Mask the FIR bit raised when an MMIO operation targets an invalid location. It's the recommendation from recent documentation and hostboot is expected to mask it at some point. In the meantime, let's play it safe. Signed-off-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-01-30npu2-hw-procedures.c: Correct phy lane mappingAlistair Popple1-3/+3
Each nvlink device is associated with a particular group of OBUS lanes via a lane mask which is read from HDAT via the device-tree. However Skiboot's interpretation of lane mask was different to what is exported from the HDAT. Specifically the lane mask bits in the HDAT are encoded in IBM bit ordering for a 24-bit wide value. So for example in normal bit ordering lane-0 is represented by having lane-mask bit 23 set and lane-23 is represented by lane-mask bit 0. This patch alters the Skiboot interpretation to match what is passed from HDAT. Signed-off-by: Alistair Popple <alistair@popple.id.au> Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Reviewed-by: Reza Arbab <arbab@linux.vnet.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-01-30npu2-hw-procedures.c: Power up lanes during ntl resetAlistair Popple1-0/+13
Newer versions of Hostboot will not power up the NVLink PHY lanes by default. The phy_reset procedure already powers up the lanes but they also need to be powered up in order to access the DL. The reset_ntl procedure is called by the device driver to bring the DL out of reset and get it into a working state. Therefore we also need to add lane and clock power up to the reset_ntl procedure. Signed-off-by: Alistair Popple <alistair@popple.id.au> Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Reviewed-by: Reza Arbab <arbab@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-01-30witherspoon: Fix VPD EEPROM typeOliver O'Halloran1-0/+20
There are userspace tools that update the planar VPD via the sysfs interface. Currently we do not get correct information from hostboot about the exact type of the EEPROM so we need to manually fix it up here. This needs to be done as a platform specific fix since there is not standardised VPD EEPROM type. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-01-30Fix xscom-utils distclean targetFrédéric Bonnard1-1/+1
In Debian/Ubuntu, the packaging system likes to have a full cleanup that restores the tree back to original one, so add some files to the distclean target. Signed-off-by: Frédéric Bonnard <frediz@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-01-30Add man pages for xscom-utils and pflashFrédéric Bonnard7-1/+167
For the need of Debian/Ubuntu packaging, I infered some initial man pages from their help output. Signed-off-by: Frédéric Bonnard <frediz@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-01-30hdata/vpd: Remove possible dereference after null check (CID 207468)Cyril Bur1-1/+1
The next_extry label doesn't do anything other than perform an addition which requires a dereference of the NULL entry variable, just continue the loop instead. Fixes: 77190aa7 (hdata/vpd: Rework vpd node creation logic) Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com> Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-01-30core: Avoid possible uninitialized pointer read (CID 209502)Cyril Bur1-1/+1
A likely copy and paste oversight. Fixes: 0d84ea6b (core: Add support for quiescing OPAL) Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-01-24PM: Fixed generation of MTSPR instruction in STOP API.Prem Shanker Jha1-1/+1
STOP API generates SPR restore instruction for a given SPR. Commit fixes the generation of mtspr instruction by API. Problem will show up only when API is changed to generate restore instruction using a GPR other than R0. CQ: SW407799 Change-Id: I2a841a9aae417b7bcd92a323197d9c6a1f3cb149 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49525 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: STEWART E. SMITH <stewart@linux.vnet.ibm.com> Dev-Ready: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49529 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-01-24Revert "libpore: Fix incorrect mtspr instruction generation"Stewart Smith1-4/+6
This reverts commit 65f9abea8e8cfd7f711a5c54217b5505826ff497. Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-01-19libstb/cvc: Register P8 secure ROM code correctlyStewart Smith1-2/+2
Register the location of the secure ROM, not the address of the location. Fixes: 594c7a6ae3ccc Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-01-14npu2.c: Add PE error detectionAlistair Popple2-18/+54
Invalid accesses from the GPU can cause a specific PE to be frozen by the NPU. Add an interrupt handler which reports the frozen PE to the operating system via as an EEH event. Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-01-14npu2.c: Fix XIVE IRQ alignmentAlistair Popple1-1/+1
Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-01-14opal/xstop: Use nvram option to enable/disable sw checkstop.Mahesh Salgaonkar1-0/+32
Add a mechanism to enable/disable sw checkstop by looking at nvram option opal-sw-xstop=<enable/disable>. For now this patch disables the sw checkstop trigger unless explicitly enabled through nvram option 'opal-sw-xstop=enable'i for p9. This will allow an opportunity to get host kernel in panic path or xmon for unrecoverable HMIs or MCE, to be able to debug the issue effectively. To enable sw checkstop in opal issue following command: # nvram -p ibm,skiboot --update-config opal-sw-xstop=enable NOTE: This is a workaround patch to disable sw checkstop by default to gain control in host kernel for better checkstop debugging. Once we have most of the checkstop issues stabilized/resolved, revisit this patch to enable sw checkstop by default. For p8 platform it will remain enabled by default unless explicitly disabled. To disable sw checkstop on p8 issue following command: # nvram -p ibm,skiboot --update-config opal-sw-xstop=disable Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> Reviewed-by: Balbir Singh <bsingharora@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-01-14Witherspoon: Remove old Witherspoon platform definitionAlistair Popple1-356/+0
An old Witherspoon platform definition was added to aid the transition from versions of Hostboot which didn't have the correct NVLink HDAT information available and/or planar VPD. These system should now be updated so remove the possibly incorrect default assumption. This may disable NVLink on old out-dated systems but it can easily be restored with the appropriate FW and/or VPD updates. In any case there is a a 50% chance the existing default behaviour was incorrect as it only supports 6 GPU systems. Using an incorrect platform definition leads to undefined behaviour which is more difficult to detect/debug than not creating the NVLink devices so remove the possibly incorrect default behaviour. Signed-off-by: Alistair Popple <alistair@popple.id.au> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Reviewed-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-01-14hdata/vpd: Fix DTC warningsOliver O'Halloran3-0/+207
All the nodes under the vpd heirachy have a unit address (their SLCA index) but no reg properties. Add them and their size/address cells to squash the warnings. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-01-14hdat/i2c: Fix SPD EEPROM compatible stringOliver O'Halloran1-1/+16
Hostboot doesn't give us accurate information about the DIMM SPD devices. Hack around by assuming any EEPROM we find on the SPD I2C master is an SPD eeprom. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-01-14hdata/i2c: Fix 512Kb EEPROM sizeOliver O'Halloran1-1/+1
There's no such thing as a 412Kb EEPROM. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-01-15SLW: fix running in mamboStewart Smith1-1/+3
Fixes: 35c66b8ce5a27ad3312806e8bde9148a5e5b5df8 Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-01-14SLW: Add p9_stop_api calls for IMCAkshay Adiga1-0/+40
Add p9_stop_api for EVENT_MASK and PDBAR scoms. These scoms are lost on wakeup from stop11. Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Reviewed-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-01-14SCOM restore for DARN and XIVEAkshay Adiga4-2/+80
While waking up from stop11, we want NCU_DARN_BAR to have enable bit set. Without this stop_api call, the value restored is without enable bit set. We loose NCU_SPEC_BAR when the quad goes into stop11, stop_api will restore while waking up from stop11. Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-01-14SLW: Call p9_stop_api only if deep_states are enabledAkshay Adiga1-0/+9
All init time p9_stop_api calls have been isolated to slw_late_init. If p9_stop_api fails, then the deep states can be excluded from device tree. For p9_stop_api called after device-tree for cpuidle is created , has_deep_states will be used to check if this call is even required. Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-01-14SLW: Detect if deep states are enabledAkshay Adiga2-1/+16
Patch adds a global variable which indicates if the deep states are enabled through stop-enabled-bits. Only applies to POWER9. Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-01-14SLW: Move MAMBO simulator checks to slw_initAkshay Adiga1-7/+2
Move MAMBO simulator checks to slw_init. Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-01-14SLW: Use wakeup_engine state to handle errors in wakeup engineAkshay Adiga2-24/+22
Patch introduces wakeup_engine_state which replaces a bool has_wakeup_engine. wakeup_engine_state can have 3 states : - WAKEUP_ENGINE_PRESENT : When everything is good. - WAKEUP_ENGINE_NOT_PRESENT : When wakeup_engine is not correctly detected. - WAKEUP_ENGINE_FAILED : If any operation on wakeup_engine failed. Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-01-14SLW: Call slw_late_init_p{8, 9} only when has_wakeup_engine is setAkshay Adiga1-14/+37
Patch adds the following changes : - Moves slw image sanity check to a seperate function called slw_image_check_p{8,9}() - Move has_wakeup_engine to global scope, so that it can be set by other functions - Code which uses wakeup_engine will only be called if sanity check passes. Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-01-14SLW: Split init functionsAkshay Adiga1-32/+43
This patch seperates code which deals with wakeup_engine from one which doesn't. Init functions for power8 and power9 are split into chip_init and late_init. slw_late_init_p?() contains wakeup_engine related code. Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-01-14SLW: Delay cpuidle device-tree creationAkshay Adiga2-1/+1
Create cpuidle device-tree after slw_init(), so that we can stop the deeper states from being added , when wakeup engine is not present or failed. Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-01-14phb4: Dump CAPP error registers when it asserts link downVaibhav Jain3-7/+38
This patch introduces a new function phb4_dump_app_err_regs() that dumps CAPP error registers in case the PEC nestfir register indicates that the fence was due to a CAPP error (BIT-24). Contents of these registers are helpful in diagnosing CAPP issues. Registers that are dumped in phb4_dump_app_err_regs() are: * CAPP FIR Register * CAPP APC Master Error Report Register * CAPP Snoop Error Report Register * CAPP Transport Error Report Register * CAPP TLBI Error Report Register * CAPP Error Status and Control Register Signed-off-by: Vaibhav Jain <vaibhav@linux.vnet.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Reviewed-by: Christophe Lombard<clombard@linux.vnet.ibm.com> Acked-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-01-05hdata: Parse IPL FW feature settingsOliver O'Halloran2-0/+54
Add parsing for the firmware feature flags in the HDAT. This indicates the settings of various parameters which are set at IPL time by firmware. Cc: stable # 5.4.x 371e88e23662 eeba2d64fb7a 0abc3af7e8f6 Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-12-22skiboot 5.9.7 release notesStewart Smith1-0/+28
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> (cherry picked from commit 2bbe8b84b87d97220809c09e8dfcf756287012e7) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-12-20lock: Add additional lock auditing codeBenjamin Herrenschmidt21-31/+106
Keep track of lock owner name and replace lock_depth counter with a per-cpu list of locks held by the cpu. This allows us to print the actual locks held in case we hit the (in)famous message about opal_pollers being run with a lock held. It also allows us to warn (and drop them) if locks are still held when returning to the OS or completing a scheduled job. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> [stewart: fix unit tests] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-12-20lock: Move cmpxchg() primitives to their own fileBenjamin Herrenschmidt2-57/+79
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-12-20Add support for new gcc 7 parametrized stack protectorBenjamin Herrenschmidt6-13/+40
This gives us per-cpu guard values as well. For now I just xor a magic constant with the CPU PIR value. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-12-20libflash/mbox-flash: fallback to requesting lower MBOX versions from BMCStewart Smith1-0/+7
Some BMC mbox implementations seem to sometimes mysteriously fail when trying to negotiate v3 when they only support v2. To work around this, we can fall back to requesting lower mbox protocol versions until we find one that works. In theory, this should already "just work", but we have a counter example, which this patch fixes. Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-12-20allow secure boot if not enforcing itStewart Smith1-6/+0
We check the secure boot containers no matter what, only *enforcing* secure boot if we're booting in secure mode. This gives us an extra layer of checking firmware is legit even when secure mode isn't enabled, as well as being really useful for testing. Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-12-20Mambo: run hello_world and sreset_world tests with Secure and Trusted BootStewart Smith10-13/+75
We *disable* the secure boot part, but we keep the verified boot part as we don't currently have container verification code for Mambo. We can run a small part of the code currently though. Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-12-18libstb/(create|print)-container: Sync with sb-signing-utilsStewart Smith15-388/+1575
The sb-signing-utils project has improved upon the skeleton create-container tool that existed in skiboot, including being able to (quite easily) create *signed* images. This commit brings in that code (and makes it build in the skiboot build environment) and updates our skiboot.*.stb generating code to use the development keys. We also update print-container as well, syncing it with the upstream project. Derived from github.com:open-power/sb-signing-utils.git at v0.3-5-gcb111c03ad7f (and yes, changes here will be submitted upstream) Cc: Dave Heller <hellerda@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-12-18doc: update libstb documentation with POWER9 changesClaudio Carvalho3-182/+181
POWER9 changes reflected in the libstb: - bumped ibm,secureboot node to v2 - added ibm,cvc node - hash-algo superseded by hw-key-hash-size Signed-off-by: Claudio Carvalho <cclaudio@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-12-18libstb/cvc: update memory-region to point to /reserved-memoryClaudio Carvalho3-1/+40
The linux documentation, reserved-memory.txt, says that memory-region is a phandle that pairs to a children of /reserved-memory. This updates /ibm,secureboot/ibm,cvc/memory-region to point to /reserved-memory/secure-crypt-algo-code instead of /ibm,hostboot/reserved-memory/secure-crypt-algo-code. Signed-off-by: Claudio Carvalho <cclaudio@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-12-18libstb: add support for ibm, secureboot-v2Claudio Carvalho3-0/+71
ibm,secureboot-v2 changes: - The Container Verification Code is represented by the ibm,cvc node. - Each ibm,cvc child describes a CVC service. - hash-algo is superseded by hw-key-hash-size. Signed-off-by: Claudio Carvalho <cclaudio@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-12-18hdata/tpmrel.c: add ibm, cvc device tree nodeClaudio Carvalho3-0/+166
In P9, the Container Verification Code is stored in a hostboot reserved memory and the list of provided CVC services is stored in the TPMREL_IDATA_HASH_VERIF_OFFSETS idata array. Each CVC service has an offset and version. This adds the ibm,cvc device tree node and its documentation. Signed-off-by: Claudio Carvalho <cclaudio@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-12-18hdata/tpmrel.c: add firmware event log info to the tpm nodeClaudio Carvalho6-1/+156
This parses the firmware event log information from the secureboot_tpm_info HDAT structure and add it to the tpm device tree node. There can be multiple secureboot_tpm_info entries with each entry corresponding to a master processor that has a tpm device, however, multiple tpm is not supported. Signed-off-by: Claudio Carvalho <cclaudio@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-12-18hdata/spira: add ibm, secureboot node in P9Claudio Carvalho2-6/+48
In P9, skiboot builds the device tree from the HDAT. These are the "ibm,secureboot" node changes compared to P8: - The Container-Verification-Code (CVC), a.k.a. ROM code, is no longer stored in a secure ROM with static address. In P9, it is stored in a hostboot reserved memory and each service provided also has a version, not only an offset. - The hash-algo property is not provided via HDAT, instead it provides the hw-key-hash-size, which is indeed the information required by the CVC to verify containers. This parses the iplparams_sysparams HDAT structure and creates the "ibm,secureboot", which is bumped to "ibm,secureboot-v2". In "ibm,secureboot-v2": - hash-algo property is superseded by hw-key-hash-size. - container verification code is explicitly described by a child node. Added in a subsequent patch. Signed-off-by: Claudio Carvalho <cclaudio@linux.vnet.ibm.com> Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Reviewed-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
generated by cgit v1.1 at 2024-10-11 12:51:48 +0000