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2020-11-03Add chip_dev_Associativity to secure-memory@ nodesultravisorRyan Grimm1-1/+2
Signed-off-by: Ryan Grimm <grimm@linux.ibm.com>
2020-11-03hdata/memory.c: Create secure-memory@ nodes from HDATRyan Grimm1-2/+4
2020-11-03tpm: Send selftest to mitigate RSA key issueMichael Anderson1-0/+27
- Send selftest to mitigate RSA key issue. Signed-off-by: Michael Anderson <andmike@linux.ibm.com>
2020-11-03uv: Add wrapping-key-handle to properties passed to uvMichael Anderson2-0/+2
- Add wrapping-key-handle property to set of properties passed to ultravisor. Signed-off-by: Michael Anderson <andmike@linux.ibm.com>
2020-11-03HACK: patching BE instruction to handle dual endianessPratik Rajesh Sampat1-0/+30
--TO BE REVERTED-- This commit patches HCODE to handle dual endianess for the SC2 instruction, Once the firmware is patched this commit must be reverted. Signed-off-by: Pratik Rajesh Sampat <psampat@linux.ibm.com>
2020-11-03self-save and self-restorePratik Rajesh Sampat13-35/+549
Signed-off-by: Ram Pai <linuxram@us.ibm.com> [merged all self-save/self-restore enabling patches] Signed-off-by: Pratik Rajesh Sampat <psampat@linux.ibm.com>
2020-11-03ultravisor: Pickup wrapkey data from mambo.Michael Anderson1-2/+56
- For testing wrapkey support pickup data from mambo. Signed-off-by: Michael Anderson <andmike@linux.ibm.com>
2020-11-03pef: Fix up handling of HB reservesRyan Grimm1-57/+7
For Hostboot, Skiboot parses secure memory from the HDAT table and creates the secure-memory-ranges property. Then, Skiboot reserves the entire secure memory region and names it ibm,secure-mem<n> where n is the nth region found. Later, Skiboot parses reserves from secure memory and if found in secure memory the reserve is split. For example: ibm,hbrt-code-image@1200ffd110000 ibm,hbrt-data@1200ffd550000 ibm,homer-image@1200ffd800000 ibm,homer-image@1200ffdc00000 ibm,occ-common-area@1200fff800000 ibm,sbe-comm@1200ffd0e0000 ibm,sbe-comm@1200ffd100000 ibm,sbe-ffdc@1200ffd0d0000 ibm,sbe-ffdc@1200ffd0f0000 ibm,secure-crypt-algo-code@1200ffd0c0000 ibm,secure-mem0@1000e00000000 ibm,secure-mem1@1200e00000000 ibm,secure-mem1@1200ffccf8000 ibm,secure-mem1@1200ffe000000 ibm,unsecure-homer@200dffe00000 ibm,uvbwlist@1200ffccf0000 For Mambo, ultra.tcl creates the secure-memory-ranges property at 8GB. Mambo has no protection on secure memory, so a watchpoint should be used to ensure Skiboot does not touch secure memory. ultra.tcl creates the ibm,secure-mem reserve. For BML, the BML script parses secure memory from the Cronus config file and creates the secure-memory-ranges proprty. In all cases, the console log should indicate secure memory has been found and added to the device tree. For example: UV: Secure memory range added to DT [0x000100fe00000000..0x001010000000000] Signed-off-by: Ryan Grimm <grimm@linux.ibm.com>
2020-11-03UV_FDT: populate the UV FDT after the password is generated.Ram Pai1-28/+39
Signed-off-by: Ram Pai <linuxram@us.ibm.com>
2020-11-03Change skiboot to support opalcreate.cClaudio Carvalho4-4/+10
Signed-off-by: Ram Pai <linuxram@us.ibm.com> [removed the WIP tag] Signed-off-by: Claudio Carvalho <cclaudio@linux.ibm.com>
2020-11-03ultravisor: Remove stb header prior to decompressMichael Anderson1-0/+3
- Remove stb header prior to decompress. Signed-off-by: Michael Anderson <andmike@linux.ibm.com>
2020-11-03Import opalcreate.c from the ibmtss projectClaudio Carvalho3-1/+1094
This patch needs to be broken down into smaller patches, such as: - Create the wrapping key - Change the password on the wrapping key - Pass the wrapping key to the ultravisor We should also do some cleanup, such as: - Remove "#ifndef __SKIBOOT__" and the inner code - Remove "#ifdef __SKIBOOT__" Signed-off-by: Ram Pai <linuxram@us.ibm.com> [remove the WIP tag] Signed-off-by: Claudio Carvalho <cclaudio@linux.ibm.com>
2020-11-03libstb: Add UV TSS.Claudio Carvalho214-26/+57905
This imports the UV TSS implementation, which is a light version of the TSS implemented by Ken Goldman. This also imports the mbedtls source coude, although we may not need it in skiboot for the TSS.
2020-11-03libstb: replace mbedtls files with v2.16.2 versionEric Richter177-215/+113757
Signed-off-by: Eric Richter <erichte@linux.ibm.com>
2020-11-02libstb/trustedboot: Map UV image measurement to PCR4Claudio Carvalho1-0/+1
This maps the ultravisor image to be measured to PCR4. The image is automatically verified and measured hen it is loaded from PNOR. Signed-off-by: Claudio Carvalho <cclaudio@linux.ibm.com>
2020-11-02occ: Disable OCC on UV systemsRyan Grimm3-1/+29
On Ultravisor enabled system, temporarily disable OCC irq paths for shared memory updates when OCC is up, so as to boot the system. We also disable the OPAL-OCC command response interface which is required for Sensors. This will be enabled at a later point when we can read the OCC Common area residing in secure memory region. Disable stop levels if they are enabled in the SPIRA. Skip pstates_init and occ_sensor_init as well. Signed-off-by: Ram Pai <linuxram@us.ibm.com> [merged all OCC fixes into a single fix] Signed-off-by: Satheesh Rajendran <sathnaga@linux.vnet.ibm.com> [Reduce occ debug log flood] Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com> Signed-off-by: Ryan Grimm <grimm@linux.ibm.com>
2020-11-02xscoms: read/write xscoms using ucallMadhavan Srinivasan3-2/+45
xscom registers are in the secure memory area when secure mode is enabled. These registers cannot be accessed directly and need to use ultravisor services using ultracall. Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> Signed-off-by: Santosh Sivaraj <santosh@fossix.org> [ linuxram: Set uv_present just after starting UV ] Signed-off-by: Ram Pai <linuxram@us.ibm.com>
2020-11-02pef: ultra-call support for skibootMadhavan Srinivasan2-1/+34
A new type of system call called the ultra call is used to get the services of the ultravisor. This ultracall support is needed in skiboot to access the xscoms which are in the secure memory area. Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> Signed-off-by: Santosh Sivaraj <santosh@fossix.org> [ andmike: ABI hange to switch from r0 to r3 ] Signed-off-by: Michael Anderson <andmike@linux.ibm.com> [ grimm: Comments to start_uv for register usage ] Signed-off-by: Ryan Grimm <grimm@linux.ibm.com>
2020-11-02pef: Add memcons support for ultravisorMadhavan Srinivasan4-6/+28
The ultravisor console buffer is provided at offset 0x01100000 from the skiboot base. Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> Signed-off-by: Santosh Sivaraj <santosh@fossix.org>
2020-11-02ifdef out tm-suspend-hypervisor-assist cpu featureRyan Grimm1-0/+2
We've tried (1) disabling TM in the host via device tree (2) disabling TM in qemu via "cap-tm=off" (3) disabling TM in guest via kernel command line but we're still getting this: [ 81.914285] Facility 'TM' unavailable (5) exception in kernel mode at c000000000140324 [ 81.914298] Oops: Unexpected facility unavailable exception, sig: 6 [#1] [ 81.914305] LE PAGE_SIZE=64K MMU=Radix MMU=Hash SMP NR_CPUS=2048 NUMA PowerNV [ 81.914312] Modules linked in: [ 81.914318] CPU: 59 PID: 1487 Comm: qemu-system-ppc Not tainted 5.3.0-rc5-46613-gcafd1c60ac88 #1 [ 81.914325] NIP: c000000000140324 LR: c00000000012afa8 CTR: c00000000012c960 [ 81.914332] REGS: c000003d5032b490 TRAP: 0f60 Not tainted (5.3.0-rc5-46613-gcafd1c60ac88) [ 81.914338] MSR: 9000000002803033 <SF,HV,VEC,VSX,FP,ME,IR,DR,RI,LE> CR: 22242242 XER: 00000000 [ 81.914349] CFAR: c00000000012afa4 IRQMASK: 3 [ 81.914349] GPR00: 0000000000000001 c000003d5032b720 c000000001791800 c000003d44900000 [ 81.914349] GPR04: 8000000000000000 0000000000000000 0000000000000000 0000000000000000 [ 81.914349] GPR08: 0000000000000001 0000000000000001 0000000000000000 00000010068e5b9c [ 81.914349] GPR12: 0000000000004000 c000003dbffcd380 0000000000000000 00007fffa92a0000 [ 81.914349] GPR16: 0000000000000000 00007fffaa5d4410 0000000000000000 0000000000000001 [ 81.914349] GPR20: c000000001966378 000000000000003b c000003d4478a558 0000000000000010 [ 81.914349] GPR24: 0000000000000000 4000000000000000 c000000000000000 0000000000000980 [ 81.914349] GPR28: c000003d50090000 004000000054f41f 0000001006a57e04 c000003d44900000 [ 81.914401] NIP [c000000000140324] kvmppc_restore_tm_hv+0x38/0x80 [ 81.914407] LR [c00000000012afa8] kvmhv_p9_guest_entry+0x108/0x910 [ 81.914412] Call Trace: [ 81.914416] [c000003d5032b720] [c00000000012afa8] kvmhv_p9_guest_entry+0x108/0x910 (unreliable) [ 81.914424] [c000003d5032b900] [c00000000012c09c] kvmhv_run_single_vcpu+0x2fc/0xbc0 [ 81.914431] [c000003d5032b9d0] [c00000000012cf80] kvmppc_vcpu_run_hv+0x620/0xb80 [ 81.914438] [c000003d5032bae0] [c000000000111664] kvmppc_vcpu_run+0x34/0x50 [ 81.914444] [c000003d5032bb00] [c00000000010db8c] kvm_arch_vcpu_ioctl_run+0x23c/0x410 [ 81.914451] [c000003d5032bb90] [c000000000100058] kvm_vcpu_ioctl+0x468/0x7c0 [ 81.914458] [c000003d5032bd00] [c000000000440de0] do_vfs_ioctl+0xe0/0xc60 [ 81.914465] [c000003d5032bdb0] [c0000000004419c4] ksys_ioctl+0x64/0xf0 [ 81.914472] [c000003d5032be00] [c000000000441a78] sys_ioctl+0x28/0x80 [ 81.914478] [c000003d5032be20] [c00000000000bae4] system_call+0x5c/0x70 [ 81.914483] Instruction dump: [ 81.914487] 60000000 7c0802a6 f8010010 38000000 980d0b28 7ca000a6 38000001 780507ce [ 81.914496] 7ca00164 e8a315e8 e8c315f8 e8e315f0 <7ca023a6> 7cc123a6 7ce223a6 7885ffa1 [ 81.914506] ---[ end trace 7ee98dd79ab5b3b0 ]--- [ 81.915662] [ 81.915684] qemu-system-ppc (1487) used greatest stack depth: 11152 bytes left Need to dig and figure out how to disable this cpu feature in the guest. Signed-off-by: Ryan Grimm <grimm@linux.ibm.com>
2020-11-02disable parition in flash dt nodeRyan Grimm1-1/+5
Signed-off-by: Ram Pai <linuxram@us.ibm.com> [fixed compilation warnings] Signed-off-by: Ryan Grimm <grimm@linux.ibm.com>
2020-11-02Add ultravisor support in OPALMadhavan Srinivasan12-2/+620
Ultravisor is the firmware which runs in the new privelege mode called ultravisor mode, which was introduced in Power 9. Ultravisor enables running of secure virtual machines on the host. Protected execution facility in Power 9 uses special memory areas designated as secure memory, which can be accessed only in the ultravisor mode. This protection is provided by the hardware. These designated memory areas are used by the guests running as secure virtual machines. The secure memory ranges are provided by the hostboot through HDATA. Get secure memory ranges from HDATA and add to device tree for ultravisor firmware. Ultravisor firmware is present as a lid file or as 'UVISOR' partition. Use flash resource load helper to load ultravisor firmware into secure memory area pointed by the hdata. The ultravisor image after is start on each CPU after being loaded from the flash/fsp. It is copied to secure memory and run. Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> Signed-off-by: Santosh Sivaraj <santosh@fossix.org> [ grimm: Add init_uv comments, logging, and logic cleanups ] [ grimm: Increase UV image max size to 2MB ] [ grimm: Redfine the OPAL UV shared data structure ] [ grimm: Remove Hostboot regions from secure range 0 ] [ grimm: SPDX licensing ] [ grimm: clean up allocation and freeing ] [ grimm: DT bindings fixups ] [ grimm: Define load identifiers for ultra.lid.xz ] [ grimm: Improve error logging ] [ grimm: Fix secure-memory-ranges for multiple ranges ] [ grimm: hdata: Dont ignore range if SMF is enbaled ] [ grimm: use cleanup_addr on secure mem ranges ] [ grimm: ret code checks, various cleanups for BML ] Signed-off-by: Ryan Grimm <grimm@linux.ibm.com> [ andmike: Split init and start of ultravisor ] Signed-off-by: Michael Anderson <andmike@linux.ibm.com>
2020-11-02Makefile.main: Remove -Werror on behalf of GCC 9Claudio Carvalho1-1/+0
GCC 9 adds the -Werror=address-of-packed-member feature. We are getting this error when compiling the hw/sbe-p9.c. This removes "-Werror" from the CFLAGS as a workaround. Please do not post this patch upstream. Signed-off-by: Ram Pai <linuxram@us.ibm.com> [removed WIP tag in the subject line] Signed-off-by: Claudio Carvalho <cclaudio@linux.ibm.com>
2020-11-02doc/opal-uv-abi.rstRyan Grimm1-0/+420
Signed-off-by: Ryan Grimm <grimm@linux.ibm.com>
2019-08-16skiboot 6.5 release notesv6.5Oliver O'Halloran1-0/+20
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-16ipmi: Use standard MIN() macro definitionJordan Niethe1-3/+1
There is a MIN() macro definition in skiboot.h. Remove the redundant definition from here and use that one. Signed-off-by: Jordan Niethe <jniethe5@gmail.com> Acked-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-16hw/phb4: Use standard MIN/MAX macro definitionsJordan Niethe1-6/+3
The max() macro definition incorrectly returns the minimum value. The max() macro is used to ensure that PERST has been asserted for 250ms and that we wait 100ms seconds for the ETU logic in the CRESET_START PHB4 PCI slot state. However, by returning the minimum value there is no guarantee that either of these requirements are met. Correct macro definitions for MIN and MAX are already provided in skiboot.h. Remove the redundant/incorrect versions here and switch to using the standard ones. Fixes: 70edcbb4b39d ("hw/phb4: Skip FRESET PERST when coming from CRESET") Signed-off-by: Jordan Niethe <jniethe5@gmail.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-16hw/phb4: Prevent register accesses when in resetOliver O'Halloran2-0/+11
While the the ETU is in reset we cannot access any of the PHB registers. If a PHB register is accessed via the XSCOM indirect interface then we'll cause an ETU reset error which may prevent the PHB from being re-initialised once the reset is lifted. Prevent register accesses while in reset by adding a flag that is set while the ETU reset bit is high and checking that flag in the XSCOM (ASB) backdoor register access path. Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-16npu: Fix device binding error messageReza Arbab1-2/+6
Helping someone troubleshoot a Garrison machine, I noticed some of the BDFs printed here are wrong: npu_dev_bind_pci_dev: No PCI device for NPU device 0004:00:00.0 to bind to. If you expect a GPU to be there, this is a problem. npu_dev_bind_pci_dev: No PCI device for NPU device 0004:00:01.0 to bind to. If you expect a GPU to be there, this is a problem. npu_dev_bind_pci_dev: No PCI device for NPU device 0004:00:04.0 to bind to. If you expect a GPU to be there, this is a problem. npu_dev_bind_pci_dev: No PCI device for NPU device 0004:00:05.0 to bind to. If you expect a GPU to be there, this is a problem. Change the prlog() call to print them correctly. Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-16npu3: Expose remaining ATSD launch registersReza Arbab2-9/+13
List all 16 ATSD registers in the device tree, not just the first 8. Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-16npu3: Initialize NPU3_SNP_MISC_CFG0Reza Arbab2-0/+11
Enable powerbus snooping here, or else MMIO to any NTL/NDL registers will cause a checkstop. This was not an issue in Simics simulation, but discovered rather quickly during bringup on a real Axone chip. Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Reviewed-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-16npu3: Rename NPU3_SM_MISC_CFGn register macrosReza Arbab2-12/+12
The SM blocks have multiple MISC_CFG registers. For example, there are both CS.SM0.MCP.MISC.CONFIG0 and CS.SM0.SNP.MISC.CONFIG0. Rename our macro for the former to more clearly reflect this and avoid a clash when the latter is added. Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Reviewed-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-16pci: Use a macro for accessing PCI BDF Function NumberJordan Niethe8-17/+18
Currently when the Function Number bits of a BDF are needed the bit operations to get it are free coded. There are many places where the Function Number is used, so make a macro to use instead of free coding it everytime. Signed-off-by: Jordan Niethe <jniethe5@gmail.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-16pci: Use a macro for accessing PCI BDF Device NumberJordan Niethe9-15/+16
Currently when the Device Number bits of a BDF are needed the bit operations to get it are free coded. There are many places where the Device Number is used, so make a macro to use instead of free coding it everytime. Signed-off-by: Jordan Niethe <jniethe5@gmail.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-16pci: Use a macro for accessing PCI BDF Bus NumberJordan Niethe9-18/+21
Currently when the Bus Number bits of a BDF are needed the bit operations to get it are free coded. There are many places where the Bus Number is used, so make a macro to use instead of free coding it everytime. Signed-off-by: Jordan Niethe <jniethe5@gmail.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-16core/pci-dt-slots: Remove duplicate PCIDBG() definitionJordan Niethe1-6/+0
PCIDBG() is already defined in pci.h, which is included by pci-dt-slot.c. It should not be defined again so remove this definition. Signed-off-by: Jordan Niethe <jniethe5@gmail.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-16include/xscom: Use the name EQ rather than EPOliver O'Halloran2-11/+15
The P9 pervasive spec uses the term "EP" to refer to the combination of an EQ chiplet and its two child EX chiplets. Nothing else seems to use the term EP and in Skiboot all the uses of the XSCOM_ADDR_P9_EP() macro are to translate the address of EQ specific SCOM registers. Change the name of our address calculation macros to match the general terminology to make what it does clearer. Cc: Anju T Sudhakar <anju@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-16include/xscom: Remove duplicate p9 definitionsOliver O'Halloran1-5/+0
These are already defined in xscom-p9-regs.h Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-16include/xscom: Remove duplicate p8 definitionsOliver O'Halloran1-40/+0
Duplicates of what's already in xscom-p8-regs.h Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-15MPIPL: Add documentationVasant Hegde6-0/+250
Document MPIPL device tree and OPAL APIs. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Ananth N Mavinakayanahalli <ananth@linux.vnet.ibm.com> [oliver: rebased] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-15MPIPL: Prepare architected registers data tagVasant Hegde1-0/+37
Post MPIPL kernel needs saved CPU register details to create vmcore/opalcore. This patch prepares CPU register data tag and add it to tags list. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> [oliver: rebased] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-15MPIPL: Reserve memory to capture architected registers dataVasant Hegde4-1/+53
- Split SPIRAH memory to accommodate architected register ntuple. Today we have 1K memory for SPIRAH and it uses 288 bytes. Lets split this into two parts : SPIRAH (756 bytes) architected register memory (256 bytes) - Update SPIRAH architected register ntuple - Calculate memory required to capture architected registers data Ideally we should use HDAT provided data (proc_dump_area->thread_size). But we are not getting this data during boot. Hence lets reserve fixed memory for architected registers data collection. - Add architected registers destination memory to reserve-memory DT node. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> [oliver: rebased] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-15MPIPL: Clear tags and metadataVasant Hegde1-0/+6
Post dump process, kernel sends FREE_PRESERVE_MEMEORY notification to OPAL. OPAL will clear metadata section and tags. Subsequent opal_mpipl_query_tag() call will return OPAL_EMPTY. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> [oliver: rebased] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-15MPIPL: Add OPAL API to query saved tagsVasant Hegde2-2/+43
Pre-MPIPL kernel saves various information required to create vmcore in metadata area and passes metadata area pointer to OPAL. OPAL will preserve this pointer across MPIPL. Post MPIPL kernel will request for saved tags via this API. Kernel also needs below tags: - Saved CPU registers data to access CPU registers - OPAL metadata area to create opalcore Format: opal_mpipl_query_tag(enum opal_mpipl_tags tag, uint64_t *tag_val) tag : OPAL_MPIPL_TAG_CPU Pointer to CPU register data content metadata area OPAL_MPIPL_TAG_OPAL Pointer to OPAL metadata area OPAL_MPIPL_TAG_KERNEL During first boot, kernel will setup its metadata area and asks OPAL to preserve metadata area pointer across MPIPL. Post MPIPL kernel calls this API to get metadata pointer and it will use that pointer to retrieve metadata and create dump. OPAL_MPIPL_TAG_BOOT_MEM During MPIPL registration kernel will specify how much memory firmware can use for Post MPIPL load. Post MPIPL petitboot kernel will query for this tag to get boot memory size. Return values: OPAL_SUCCESS : Operation success OPAL_PARAMETER : Invalid parameter Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> [oliver: rebased] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-15MPIPL: Prepare OPAL data tagVasant Hegde2-0/+81
Post MPIPL kernel needs OPAL metadata to create opalcore. This patch sets up OPAL metadata tag. Next patch will add API to pass metadata pointer to kernel. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> [oliver: rebased] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-15hdata: Add "mpipl-boot" property to "dump" nodeVasant Hegde2-0/+47
During MPIPL boot, hostboot updates HDAT to indicate its MPIPL boot. Lets add "mpipl-boot" property to device tree. So that kernel can detect its MPIPL boot and create dump. Device tree property: /ibm,opal/dump/mpipl-boot - Indicate kernel that its MPIPL boot Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> [oliver: rebased] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-15platform: Introduce new reboot typeVasant Hegde3-0/+14
Enhance reboot2 call to support MPIPL. Payload will call this interface to initiate MPIPL. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> [oliver: rebased] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-15HIOMAP: Reset bmc mbox in MPIPL pathVasant Hegde10-4/+251
During boot SBE and early hostboot does not use HIOMAP protocol to get image from PNOR. Instead it expects PNOR TOC and Hostboot Boot Loader to be available at particular address in LPC bus. mbox daemon in BMC side takes care of this during normal boot. Once boot is complete mbox daemon switches to normal mode. During normal reboot, BMC side mbox daemon gets notification and takes care of loading PNOR TOC and HBBL to LPC bus again. In MPIPL path, OPAL calls SBE S0 interrupt to initiate MPIPL. BMC will not be aware of this. But SBE expects PNOR TOC and HBBL to be available in LPC bus at predefined address. Hence call HIOMAP Reset from OPAL in assert path. This needs working LPC and IPMI driver in OPAL. If we have issue in these drivers then we may not be able to reset BMC MBOX properly. Hence MPIPL may fail. We have to live with this until we find a way to intiate BMC on MPIPL. CC: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> [oliver: rebased] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-15MPIPL: Save crashing PIRVasant Hegde3-0/+14
Crashing CPU PIR is required to get proper backtrace from core file. Save crashing CPU PIR before triggering MPIPL. Post MPIPL OPAL will pass saved PIR to kernel and kernel will use that to create OPAL dump. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> [oliver: rebased] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-15MPIPL: Add support to trigger MPIPL on BMC systemVasant Hegde3-3/+84
On FSP based system we call 'attn' instruction. FSP detects attention and initiates memory preserving IPL. On BMC system we have to call SBE S0 interrupt to initiate memory preserving IPL. This patch adds support to call SBE S0 interrupt in assert path. Sequence : - S0 interrupt on secondary chip SBE - S0 interrupt on primary chip SBE Note that this is hooked to ipmi_terminate path. We have HDAT flag for MPIPL support. If MPIPL is not supported then we don't create 'ibm,opal/dump' node and we will fall back to existing termination flow. Finally we want to log error log to BMC before triggerring MPIPL. Hence this patch re-organizes ipmi_terminate() such that we call ipmi_log_terminate_event() before triggering MPIPL. Note: - At present we do not have a proper way to detect SBE is alive or not. So we wait for predefined time and then call normal reboot. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> [oliver: rebased] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
generated by cgit v1.1 at 2024-06-28 14:27:24 +0000