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2018-05-28skiboot 5.9.9 release notesv5.9.9skiboot-5.9.xStewart Smith1-0/+27
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2018-04-29OPAL_PCI_SET_POWER_STATE: fix locking in error pathsStewart Smith1-4/+12
Otherwise we could exit OPAL holding locks, potentially leading to all sorts of problems later on. Cc: stable # 5.3+ Fixes: 7a3e2c4ee3aa0 Signed-off-by: Stewart Smith <stewart@linux.ibm.com> (cherry picked from commit a22ba4576ad35dccb86622e71442794d09e62bce) Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2018-02-19stb: Put correct label (for skiboot) into containerStewart Smith2-4/+10
Hostboot will expect the label field of the stb header to contain "PAYLOAD" for skiboot or it will fail to load and run skiboot. The failure looks something like this: 53.40896|ISTEP 20. 1 - host_load_payload 53.65840|secure|Secureboot Failure plid = 0x90000755, rc = 0x1E07 53.65881|System shutting down with error status 0x1E07 53.67547|================================================ 53.67954|Error reported by secure (0x1E00) PLID 0x90000755 53.67560| Container's component ID does not match expected component ID 53.67561| ModuleId 0x09 SECUREBOOT::MOD_SECURE_VERIFY_COMPONENT 53.67845| ReasonCode 0x1e07 SECUREBOOT::RC_ROM_VERIFY 53.67998| UserData1 : 0x0000000000000000 53.67999| UserData2 : 0x0000000000000000 53.67999|------------------------------------------------ 53.68000| Callout type : Procedure Callout 53.68000| Procedure : EPUB_PRC_HB_CODE 53.68001| Priority : SRCI_PRIORITY_HIGH 53.68001|------------------------------------------------ 53.68002| Callout type : Procedure Callout 53.68003| Procedure : EPUB_PRC_FW_VERIFICATION_ERR 53.68003| Priority : SRCI_PRIORITY_HIGH 53.68004|------------------------------------------------ Reported-by: Pridhiviraj Paidipeddi <ppaidipe@linux.vnet.ibm.com> Tested-by: Pridhiviraj Paidipeddi <ppaidipe@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-02-19libstb/(create|print)-container: Sync with sb-signing-utilsStewart Smith15-388/+1575
The sb-signing-utils project has improved upon the skeleton create-container tool that existed in skiboot, including being able to (quite easily) create *signed* images. This commit brings in that code (and makes it build in the skiboot build environment) and updates our skiboot.*.stb generating code to use the development keys. We also update print-container as well, syncing it with the upstream project. Derived from github.com:open-power/sb-signing-utils.git at v0.3-5-gcb111c03ad7f (and yes, changes here will be submitted upstream) Cc: Dave Heller <hellerda@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-01-09lpc: Clear pending IRQs at bootOliver O'Halloran1-0/+4
When we come in from hostboot the LPC master has the bus reset indicator set. This error isn't handled until the host kernel unmasks interrupts, at which point we get the following suprious error: [ 20.053560375,3] LPC: Got LPC reset on chip 0x0 ! [ 20.053564560,3] LPC[000]: Unknown LPC error Error address reg: 0x00000000 Fix this by clearing the various error bits in the LPC status register before we initalise the skiboot LPC bus driver. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> (cherry picked from commit 7fb517898f69ea008077297617e1035827e29417) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-01-05hdata: Parse IPL FW feature settingsv5.9.8Oliver O'Halloran2-0/+54
Add parsing for the firmware feature flags in the HDAT. This indicates the settings of various parameters which are set at IPL time by firmware. Cc: stable # 5.4.x 371e88e23662 eeba2d64fb7a 0abc3af7e8f6 Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> (cherry picked from commit 4e23b42d2ad76da21422a1d2de471df29f76b8df) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-12-22skiboot 5.9.7 release notesv5.9.7Stewart Smith1-0/+28
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-12-21phb4: Change PCI MMIO timersMichael Neuling1-2/+2
Currently we have a mismatch between the NCU and PCI timers for MMIO accesses. The PCI timers must be lower than the NCU timers otherwise it may cause checkstops. This changes PCI timeouts controlled by skiboot to 33-50ms. It should be forwards and backwards compatible with expected hostboot changes to the NCU timer. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> (cherry picked from commit 5cee066746d238feef51dd7b0359c3456b089748) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-12-19p8-i2c: Limit number of retry attemptsOliver O'Halloran2-2/+11
Current we will attempt to start an I2C transaction until it succeeds. In the event that the OCC does not release the lock on an I2C bus this results in an async token being held forever and the kernel thread that started the transaction will block forever while waiting for an async completion message. Fix this by limiting the number of attempts to start the transaction. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> (cherry picked from commit c2e404aedd52da91fdf605e24b9d1ae7894974c5) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-12-15skiboot 5.9.6 release notesv5.9.6Stewart Smith1-0/+30
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-12-13sensors: occ: Skip counter type of sensorsShilpasri G Bhat1-0/+3
Don't add counter type of sensors to device-tree as they don't fit into hwmon sensor interface. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> (cherry picked from commit 275efcc44fdad3572e6180f625d356c8b7cca68d) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-12-13SCOM Restore: Increased the EQ SCOM restore limit.Prem Shanker Jha1-1/+16
Commit increases the SCOM restore limit from 16 to 31. HW-Image-Prereq: I781b0862dc983001574ba5f09a84ea0a2f7f781f HW-ImageBuild-Prereq: I43e7e067b59513db1c99ce913009a9a3ef5de90b CQ:HW423686 Change-Id: Ied6c919ff88870cd71319854a2b6aebbcc591af1 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49055 Dev-Ready: Gregory S. Still <stillgs@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> (cherry picked from hostboot https://ralgit01.raleigh.ibm.com/gerrit1/#/c/49059/ ) [stewart: I am told that this is a safe thing to cherry-pick now, even before it hits hostboot master, as hostboot and HCODE have a dependency] CC: stable Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> (cherry picked from commit 43c966bdad4613de1fb41093edc4ddaa41b7211f) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-12-14p9_stop_api: PM: Added support for version control in SCOM restore entries.Prem Shanker Jha2-4/+73
- adds version info in SCOM restore entry header - adds version specific details in SCOM restore entry header - retains old behavior of SGPE Hcode's base version Key_Cronus_Test=NO_TEST CQ:HW423686 HW-Image-Prereq: Ie1611b009e95192a0dad3a47af14ef8a36dd454b Change-Id: I43e7e067b59513db1c99ce913009a9a3ef5de90b Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48856 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Dev-Ready: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48859 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> (cherry picked from hostboot commit 47c3bbe42264514a25e00820cac1c8488aed9073) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> (cherry picked from commit c4ff9557e99a9bb0fa7e771853beb0efc4c09b1d) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-12-14p9_stop_api: EQ SCOM Restore: Introduced version control in SCOM restore entry.Prem Shanker Jha1-2/+1
- introduces version control in header of SCOM restore entry - ensures backward compatibility - introduces flexibility to handle any number of SCOM restore entry. Key_Cronus_Test=NO_TEST CQ:HW423686 HW-Image-Prereq: Ie1611b009e95192a0dad3a47af14ef8a36dd454b Change-Id: I781b0862dc983001574ba5f09a84ea0a2f7f781f Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48793 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48795 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> (cherry picked from hostboot commit 04846f139458c34b6b35824f2a63876fe75daf06) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> (cherry picked from commit 1156b5f04b3e2724ccf4af415c10ea6e8af089ea) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-12-14opal/xscom: Add recovery for lost core wakeup scom failures.Mahesh Salgaonkar2-3/+85
Due to a hardware issue where core responding to scom was delayed due to thread reconfiguration, leaves the SCOM logic in a state where the subsequent scom to that core can get errors. This is affected for Core PC scom registers in the range of 20010A80-20010ABF The solution is if a xscom timeout occurs to one of Core PC scom registers in the range of 20010A80-20010ABF, a clearing scom write is done to 0x20010800 with data of '0x00000000' which will also get a timeout but clears the scom logic errors. After the clearing write is done the original scom operation can be retried. The scom timeout is reported as status 0x4 (Invalid address) in HMER[21-23]. Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> (cherry picked from commit 10f0a09239ddfd4faf47d792f04d3124fb347f88) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-12-14opal/xscom: Move the delay inside xscom_reset() function.Mahesh Salgaonkar1-18/+21
So caller of xscom_reset() does not have to bother about adding a delay separately. Instead caller can control whether to add a delay or not using second argument to xscom_reset(). Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> Reviewed-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com> (cherry picked from commit 363f328fbc597a5996fc3b28e509c09f2869888f) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-12-13skiboot 5.9.5 Release Notesv5.9.5Stewart Smith1-0/+77
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-12-13external/test: make stripping out version number more robustStewart Smith1-2/+2
For some bizarre reason, Travis started failing on this substitution when there'd been zero code changes in this area... This at least papers over whatever the problem is for the time being. Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> (cherry picked from commit 41f51c834a1be508ca2e7446fe8fa6abc3af473c) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-12-13timer: Stop calling list_top() racilyBenjamin Herrenschmidt1-4/+5
This will trip the debug checks in debug builds under some circumstances and is actually a rather bad idea as we might look at a timer that is concurrently being removed and modified, and thus incorrectly assume there is no work to do. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> (cherry picked from commit b504f2737e9ba3b6935b4ea1c015b3643aefaf51) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-12-12xive: Ensure VC informational FIRs are maskedBenjamin Herrenschmidt2-0/+11
Some HostBoot versions leave those as checkstop, they are harmless and can sometimes occur during normal operations. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Tested-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> (cherry picked from commit 84febad7c5f947d744ef656f4b478d8b1df51471) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-12-12xive: Fix occasional VC checkstops in xive_resetBenjamin Herrenschmidt1-3/+54
The current workaround for the scrub bug described in __xive_cache_scrub() has an issue in that it can leave dirty invalid entries in the cache. When cleaning up EQs or VPs during reset, if we then remove the underlying indirect page for these entries, the XIVE will checkstop when trying to flush them out of the cache. This replaces the existing workaround with a new pair of workarounds for VPs and EQs: - The VP one does the dummy watch on another entry than the one we scrubbed (which does the job of pushing old stores out) using an entry that is known to be backed by a permanent indirect page. - The EQ one switches to a more efficient workaround which consists of doing a non-side-effect ESB load from the EQ's ESe control bits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> (cherry picked from commit 1e00d546ca29d5eb9c51558250aa37facf8f2afb) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-12-12io: Add load_wait() helperBenjamin Herrenschmidt1-0/+8
This uses the standard form twi/isync pair to ensure a load is consumed by the core before continuing. This can be necessary under some circumstances for example when having the following sequence: - Store reg A - Load reg A (ensure above store pushed out) - delay loop - Store reg A IE, a mandatory delay between 2 stores. In theory the first store is only guaranteed to rach the device after the load from the same location has completed. However the processor will start executing the delay loop without waiting for the return value from the load. This construct enforces that the delay loop isn't executed until the load value has been returned. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> (cherry picked from commit 238ef01e330fb3d1b180e9d0c1431d3d93d7c5f7) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-12-12xive: Do not return a trigger page for an escalation interruptBenjamin Herrenschmidt1-2/+2
This is bogus, we don't support them. (Thankfully the callers didn't actually try to use this on escalation interrupts). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Tested-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> (cherry picked from commit 3e7f04a7398a5dcb38ff11d0b11f630630a3bb74) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-12-12xive: Mark a freed IRQ's IVE as valid and maskedBenjamin Herrenschmidt1-1/+1
Removing the valid bit means a FIR will trip if it's accessed inadvertently. Under some circumstances, the XIVE will speculatively access an IVE for a masked interrupt and trip it. So make sure that freed entries are still marked valid (but masked). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Tested-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> (cherry picked from commit 2d98b41e4c30bc82ea61ceaa6cf1f895563b4cf1) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-12-13hw/nx: Fix NX BAR assignmentsOliver O'Halloran2-27/+46
The NX rng BAR is used by each core to source random numbers for the DARN instruction. Currently we configure each core to use the NX rng of the chip that it exists on. Unfortunately, the NX can be deconfigured by hostboot and in this case we need to use the NX of a different chip. This patch moves the BAR assignments for the NX into the normal nx-rng init path. This lets us check if the normal (chip local) NX is active when configuring which NX a core should use so that we can fallback gracefully. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> (cherry picked from commit ac685bccd8899b6021f6441551e845151a9a1b94) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-29skiboot 5.9.4 release notesv5.9.4Stewart Smith1-0/+26
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-28npu2: hw-procedures: Change phy_rx_clock_sel valuesReza Arbab1-4/+4
The clock selection bits we set here are inputs to a state machine. DL clock select (bits 30-31) 0b00: lane 0 clock 0b01: lane 7 clock 0b10: grid clock 0b11: invalid/noop To recover from a potential glitch, we need to ensure that the value we set forces a state change. Our current sequence is to set 0x3 followed by 0x1. With the above now known, that is actually a noop followed by selection of lane 7. Depending on lane reversal, that selection is not a state change for some bricks. The way to force a state change in all cases is to switch to the grid clock, and then back to a lane. Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> Acked-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> (cherry picked from commit 878c718aed200cc2b6b7c6bca3a6e2fa2351ec95) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-28npu2: hw-procedures: Manipulate IOVALID during trainingReza Arbab1-0/+24
Ensure that the IOVALID bit for this brick is raised at the start of link training, in the reset_ntl procedure. Then, to protect us from a glitch when the PHY clock turns off or gets chopped, lower IOVALID for the duration of the phy_reset and phy_rx_dccal procedures. Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> Acked-By: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> (cherry picked from commit 4e04c833a1d460d706d9c4fec16a951d75a52efb) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-28npu2: hw-procedures: Add obus_brick_index()Reza Arbab1-16/+13
We have code in reset_ntl() which finds the index number of our brick within its obus chiplet. Move that logic to a separate function for reuse. No functional change. Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> Acked-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> (cherry picked from commit e6b5867adb7fa18f9f04bfc4c4dde3b7769bf0e4) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-22skiboot 5.9.3 release notesv5.9.3Stewart Smith1-0/+24
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-21npu2: hw-procedures: Add check_credits procedureReza Arbab2-1/+39
As an immediate mitigator for a current hardware glitch, add a procedure that can be used to validate NTL credit values. This will be called as a safeguard to check that link training succeeded. Assert that things are exactly as we expect, because if they aren't, the system will experience a catastrophic failure shortly after the start of link traffic. Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> Acked-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> (cherry picked from commit a752f2d908d1fd3d95cedf2b952729995ce53234) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-21npu2: Print bdfn in NPU2DEV* logging macrosReza Arbab1-3/+8
Revise the NPU2DEV{DBG,INF,ERR} logging macros to include the device's bdfn. It's useful to know exactly which link we're referring to. For instance, instead of [ 234.044921238,6] NPU6: Starting procedure reset_ntl [ 234.048578101,6] NPU6: Starting procedure reset_ntl [ 234.051049676,6] NPU6: Starting procedure reset_ntl [ 234.053503542,6] NPU6: Starting procedure reset_ntl [ 234.057182864,6] NPU6: Starting procedure reset_ntl [ 234.059666137,6] NPU6: Starting procedure reset_ntl we'll get [ 234.044921238,6] NPU6:0:0.0 Starting procedure reset_ntl [ 234.048578101,6] NPU6:0:0.1 Starting procedure reset_ntl [ 234.051049676,6] NPU6:0:0.2 Starting procedure reset_ntl [ 234.053503542,6] NPU6:0:1.0 Starting procedure reset_ntl [ 234.057182864,6] NPU6:0:1.1 Starting procedure reset_ntl [ 234.059666137,6] NPU6:0:1.2 Starting procedure reset_ntl Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> Acked-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> (cherry picked from commit 1c5417ec1898dbdd072495913d7fbc657e570e6f) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-16skiboot 5.9.2 release notesv5.9.2Stewart Smith1-0/+80
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-15phb4: Fix lane equalisation settingMichael Neuling1-1/+1
Fix cut and paste from phb3. The sizes have changes now we have GEN4, so the check here needs to change also Without this we end up with the default settings (all '7') rather than what's in HDAT. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> (cherry picked from commit d957e9278994831831f0bfa7d13433da4b36b4de) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-15hdata: Fix copying GEN4 lane equalisation settingsMichael Neuling1-0/+2
These aren't copied currently but should be. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> (cherry picked from commit 4e74625dc9f1e1d080128203dc410ff0027c4fcf) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-15phb4: Fix PE mapping of M32 BARBenjamin Herrenschmidt1-13/+11
The M32 BAR is the PHB4 region used to map all the non-prefetchable or 32-bit device BARs. It's supposed to have its segments remapped via the MDT and Linux relies on that to assign them individual PE#. However, we weren't configuring that properly and instead used the mode where PE# == segment#, thus causing EEH to freeze the wrong device or PE#. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> (cherry picked from commit 4002ea166fde4b4e44f6571027c60c6b75df5c33) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-15phb4: Fix lost bit in PE number on config accessesBenjamin Herrenschmidt1-3/+3
A PE number can be up to 9 bits, using a uint8_t won't fly.. That was causing error on config accesses to freeze the wrong PE. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> (cherry picked from commit a1cd5529a84ccf3c88e12a864705e4de93908d8e) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-15npu2: Move to new GPU memory mapMichael Neuling5-5/+65
There are three different ways we configure the MCD and memory map. 1) Old way (current way) Skiboot configures the MCD and puts GPUs at 4TB and below 2) New way with MCD Hostboot configures the MCD and skiboot puts GPU at 4TB and above 3) New way without MCD No one configures the MCD and skiboot puts GPU at 4TB and below The patch keeps option 1 and adds options 2 and 3. The different configurations are detected using certain scoms (see patch). Option 1 will go away eventually as it's a configuration that can cause xstops or data integrity problems. We are keeping it around to support existing hostboot. Option 2 supports only 4 GPUs and 512GB of memory per socket. Option 3 supports 6 GPUs and 4TB of memory but may have some performance impact. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> (cherry picked from commit c76636f3d73fbbc3a1f56ca085eb80f9e56d0411) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-15phys-map: Rename GPU_MEM to GPU_MEM_4T_DOWNMichael Neuling3-12/+12
This map is soon to be replaced, but we are going to keep it around for a little while so that we support older hostboot firmware. Rename it for now. Signed-off-by: Michael Neuling <mikey@neuling.org> Reviewed-by: Balbir Singh <bsingharora@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> (cherry picked from commit 74d9a50ac2a79d39b07bbe7d7e0bbb72f7f5b026) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-15npu2: MCD refactorMichael Neuling1-13/+20
Pull out MCD writing code into npu2_mcd_init() No functional change. Signed-off-by: Michael Neuling <mikey@neuling.org> Acked-by: Balbir Singh <bsingharora@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> (cherry picked from commit 75371796ac595a4ce2f1b6bd254f5f3ad7416a96) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-15npu2: Refactor BAR setting codeMichael Neuling2-6/+8
This refactors the BAR setting code to make it clearer and handle a larger range of BAR addresses. This is needed as we are about to move the GPU to a physical address that is currently not supported by this code. This change derives group and chip sections of the BAR from the base address rather than the chip_id now. mem sel is also derived from the base address, rather than assuming 0. No functional change. Signed-off-by: Michael Neuling <mikey@neuling.org> Reviewed-by: Balbir Singh <bsingharora@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> (cherry picked from commit 3c0408ded5a14e110c8a418be305ac20714cb32d) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-15npu2: Create npu2_write_mcd()Michael Neuling2-8/+19
This code is replicated, so let's put it in a function. Also add some cleanups. No functional change. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> (cherry picked from commit 4f4bf83128c1d944782f02b238e632ed8d2451af) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-14p8-i2c: Don't write the watermark register at initOliver O'Halloran1-12/+8
On P9 the I2C master is shared with the OCC. Currently the watermark values are set once at init time which is bad for two reasons: a) We don't take the OCC master lock before setting it. Which may cause issues if the OCC is currently using the master. b) The OCC might change the watermark levels and we need to reset them. Change this so that we set the watermark value when a new transaction is started rather than at init time. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> (cherry picked from commit d0f06269ed3cd3e09a9b04c5f70cb3d53a77a689) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-14phb4: Update initsMichael Neuling1-1/+1
New init value from HW folks for the fence enable register. This clears bit 17 (CFG Write Error CA or UR response) and bit 22 (MMIO Write DAT_ERR Indication) and sets bit 21 (MMIO CFG Pending Error) Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> (cherry picked from commit 560eb231d6bf36442cb467b6d63e2c5342c34dd8) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-14skiboot 5.9.1 release notesv5.9.1Stewart Smith1-0/+29
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-13npu2: hw-procedures: Refactor reset_ntl procedureReza Arbab1-15/+58
Change the implementation of reset_ntl to match the latest programming guide documentation. Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> Reviewed-by: Balbir Singh <bsingharora@gmail.com> Reviewed-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> (cherry picked from commit 30ea08acc2538869229bcdeb0ec79eedc5557e94) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-13npu2: hw-procedures: Add phy_rx_clock_sel()Reza Arbab2-1/+20
Change the RX clk mux control to be done by software instead of HW. This avoids glitches caused by changing the mux setting. Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> Reviewed-By: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> (cherry picked from commit ac6f1599ff330fa602b3c9557a08f31f1158a55f) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-13npu2: Add npu2_write_mask_4b()Reza Arbab2-0/+12
Add a 4-byte version of npu2_write_mask(). Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> Reviewed-by: Alistair Popple <alistair@popple.id.au> Reviewed-by: Balbir Singh <bsingharora@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> (cherry picked from commit d6f2505b15422e3c63932a67278ebdbca67047d5) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-10xive: Fix ability to clear some EQ flagsBenjamin Herrenschmidt1-0/+4
We could never clear "unconditional notify" and "escalate" Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> (cherry picked from commit 7c2a76705674a6594462b859d1ac5affcde96593) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-10xive: Update inits for DD2.0Benjamin Herrenschmidt2-7/+47
This updates some inits based on information from the HW designers. This includes enabling some new DD2.0 features that we don't yet exploit. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> (cherry picked from commit 484d26fd6e65b00f746f852bccb460fef7b695e0) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
generated by cgit v1.1 at 2024-10-18 17:37:44 +0000