diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/npu2-regs.h | 5 | ||||
| -rw-r--r-- | include/npu2.h | 2 | ||||
| -rw-r--r-- | include/pau-regs.h | 24 | ||||
| -rw-r--r-- | include/pau.h | 2 | ||||
| -rw-r--r-- | include/xscom-p10-regs.h | 3 |
5 files changed, 35 insertions, 1 deletions
diff --git a/include/npu2-regs.h b/include/npu2-regs.h index 22f58a6..cb1d395 100644 --- a/include/npu2-regs.h +++ b/include/npu2-regs.h @@ -610,6 +610,11 @@ void npu2_scom_write(uint64_t gcid, uint64_t scom_base, #define NPU2_TOTAL_FIR_REGISTERS 3 +#define NPU2_FIR(n) (0x2c00 + (n) * 0x40) +#define NPU2_FIR_MASK(n) (0x2c03 + (n) * 0x40) +#define NPU2_FIR_ACTION0(n) (0x2c06 + (n) * 0x40) +#define NPU2_FIR_ACTION1(n) (0x2c07 + (n) * 0x40) + /* * Can't use enums for 64 bit values, use #defines */ diff --git a/include/npu2.h b/include/npu2.h index 23b06b4..a12bf98 100644 --- a/include/npu2.h +++ b/include/npu2.h @@ -241,7 +241,7 @@ int64_t npu2_freeze_status(struct phb *phb __unused, uint8_t *freeze_state, uint16_t *pci_error_type __unused, uint16_t *severity __unused); -void npu2_dump_scoms(int chip_id); +void npu2_dump_scoms(struct npu2 *npu, int chip_id); int64_t npu2_init_context(struct phb *phb, uint64_t msr, uint64_t bdf); int64_t npu2_destroy_context(struct phb *phb, uint64_t bdf); diff --git a/include/pau-regs.h b/include/pau-regs.h index 19b0b7c..b852a5b 100644 --- a/include/pau-regs.h +++ b/include/pau-regs.h @@ -48,6 +48,17 @@ #define PAU_MCP_MISC_CFG0_MA_MCRESP_OPT_WRP PPC_BIT(9) #define PAU_MCP_MISC_CFG0_ENABLE_PBUS PPC_BIT(26) #define PAU_MCP_MISC_CFG0_OCAPI_MODE PPC_BITMASK(44, 48) +#define PAU_MCP_MISC_CERR_MESSAGE0 (PAU_BLOCK_CQ_SM(0) + 0x030) +#define PAU_MCP_MISC_CERR_MESSAGE1 (PAU_BLOCK_CQ_SM(0) + 0x038) +#define PAU_MCP_MISC_CERR_MESSAGE2 (PAU_BLOCK_CQ_SM(0) + 0x040) +#define PAU_MCP_MISC_CERR_MESSAGE3 (PAU_BLOCK_CQ_SM(0) + 0x048) +#define PAU_MCP_MISC_CERR_MESSAGE4 (PAU_BLOCK_CQ_SM(0) + 0x050) +#define PAU_MCP_MISC_CERR_MESSAGE5 (PAU_BLOCK_CQ_SM(0) + 0x058) +#define PAU_MCP_MISC_CERR_MESSAGE6 (PAU_BLOCK_CQ_SM(0) + 0x060) +#define PAU_MCP_MISC_CERR_MESSAGE7 (PAU_BLOCK_CQ_SM(0) + 0x068) +#define PAU_MCP_MISC_CERR_FIRST0 (PAU_BLOCK_CQ_SM(0) + 0x078) +#define PAU_MCP_MISC_CERR_FIRST1 (PAU_BLOCK_CQ_SM(0) + 0x080) +#define PAU_MCP_MISC_CERR_FIRST2 (PAU_BLOCK_CQ_SM(0) + 0x088) #define PAU_SNP_MISC_CFG0 (PAU_BLOCK_CQ_SM(0) + 0x180) #define PAU_SNP_MISC_CFG0_ENABLE_PBUS PPC_BIT(2) #define PAU_SNP_MISC_CFG0_OCAPI_MODE PPC_BITMASK(32, 36) @@ -79,6 +90,11 @@ #define PAU_CTL_MISC_MMIOPA_CONFIG(brk) (PAU_BLOCK_CQ_CTL + 0x098 + (brk) * 8) #define PAU_CTL_MISC_MMIOPA_CONFIG_BAR_ADDR PPC_BITMASK(1, 35) #define PAU_CTL_MISC_MMIOPA_CONFIG_BAR_SIZE PPC_BITMASK(39, 43) +#define PAU_CTL_MISC_CERR_MESSAGE0 (PAU_BLOCK_CQ_CTL + 0x0C0) +#define PAU_CTL_MISC_CERR_MESSAGE1 (PAU_BLOCK_CQ_CTL + 0x0C8) +#define PAU_CTL_MISC_CERR_MESSAGE2 (PAU_BLOCK_CQ_CTL + 0x0D0) +#define PAU_CTL_MISC_CERR_FIRST0 (PAU_BLOCK_CQ_CTL + 0x0D8) +#define PAU_CTL_MISC_CERR_FIRST1 (PAU_BLOCK_CQ_CTL + 0x0E0) #define PAU_CTL_MISC_FENCE_CTRL(brk) (PAU_BLOCK_CQ_CTL + 0x108 + (brk) * 8) #define PAU_CTL_MISC_FENCE_REQUEST PPC_BITMASK(0, 1) #define PAU_CTL_MISC_CFG_ADDR(brk) (PAU_BLOCK_CQ_CTL + 0x250 + (brk) * 8) @@ -93,6 +109,9 @@ /* CQ_DAT block registers */ #define PAU_DAT_MISC_CFG1 (PAU_BLOCK_CQ_DAT + 0x008) #define PAU_DAT_MISC_CFG1_OCAPI_MODE PPC_BITMASK(40, 44) +#define PAU_DAT_MISC_CERR_ECC_HOLD (PAU_BLOCK_CQ_DAT + 0x020) +#define PAU_DAT_MISC_CERR_ECC_MASK (PAU_BLOCK_CQ_DAT + 0x028) +#define PAU_DAT_MISC_CERR_ECC_FIRST (PAU_BLOCK_CQ_DAT + 0x030) /* OTL block registers */ #define PAU_OTL_MISC_CFG0(brk) (PAU_BLOCK_OTL(brk) + 0x000) @@ -102,6 +121,7 @@ #define PAU_OTL_MISC_CFG0_ENABLE_4_0 PPC_BIT(51) #define PAU_OTL_MISC_CFG0_XLATE_RELEASE PPC_BIT(62) #define PAU_OTL_MISC_CFG0_ENABLE_5_0 PPC_BIT(63) +#define PAU_OTL_MISC_ERR_RPT_HOLD0(brk) (PAU_BLOCK_OTL(brk) + 0x030) #define PAU_OTL_MISC_CFG_TLX_CREDITS(brk) (PAU_BLOCK_OTL(brk) + 0x050) #define PAU_OTL_MISC_CFG_TLX_CREDITS_VC0 PPC_BITMASK(0, 7) #define PAU_OTL_MISC_CFG_TLX_CREDITS_VC1 PPC_BITMASK(8, 15) @@ -118,6 +138,10 @@ #define PAU_OTL_MISC_CFG_TX_TEMP2_RATE PPC_BITMASK(16, 19) #define PAU_OTL_MISC_CFG_TX_TEMP3_RATE PPC_BITMASK(20, 23) #define PAU_OTL_MISC_CFG_TX_CRET_FREQ PPC_BITMASK(32, 34) +#define PAU_OTL_MISC_OTL_REM0(brk) (PAU_BLOCK_OTL(brk) + 0x068) +#define PAU_OTL_MISC_ERROR_SIG_RXI(brk) (PAU_BLOCK_OTL(brk) + 0x070) +#define PAU_OTL_MISC_ERROR_SIG_RXO(brk) (PAU_BLOCK_OTL(brk) + 0x078) +#define PAU_OTL_MISC_ERR_RPT_HOLD1(brk) (PAU_BLOCK_OTL(brk) + 0x0B0) #define PAU_OTL_MISC_PSL_DSISR_AN(brk) (PAU_BLOCK_OTL_PSL(brk) + 0x000) #define PAU_OTL_MISC_PSL_DAR_AN(brk) (PAU_BLOCK_OTL_PSL(brk) + 0x008) #define PAU_OTL_MISC_PSL_TFC_AN(brk) (PAU_BLOCK_OTL_PSL(brk) + 0x010) diff --git a/include/pau.h b/include/pau.h index b6fabe7..547c193 100644 --- a/include/pau.h +++ b/include/pau.h @@ -189,4 +189,6 @@ static inline uint64_t pau_read(struct pau *pau, uint64_t reg) return pau_scom_read(pau, reg, PAU_MISC_DA_LEN_8B); } +void pau_opencapi_dump_scoms(struct pau *pau); + #endif /* __PAU_H */ diff --git a/include/xscom-p10-regs.h b/include/xscom-p10-regs.h index 21ac21f..5ca4703 100644 --- a/include/xscom-p10-regs.h +++ b/include/xscom-p10-regs.h @@ -15,6 +15,9 @@ #define P10_NX_DMA_ENGINE_FIR 0x02011100 /* DMA & Engine FIR Data Register */ #define P10_NX_PBI_FIR 0x02011080 /* PowerBus Interface FIR Register */ +/* pMisc Receive Malfunction Alert Register */ +#define P10_MALFUNC_ALERT 0x00090022 + #define P10_EC_CORE_THREAD_STATE 0x412 /* XXX P10 is this right? */ #define P10_THREAD_STOPPED(t) PPC_BIT(56 + (t)) |