diff options
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/Makefile.inc | 3 | ||||
| -rw-r--r-- | hw/nx-842.c | 212 | ||||
| -rw-r--r-- | hw/nx-crypto.c | 277 | ||||
| -rw-r--r-- | hw/nx-rng.c | 99 | ||||
| -rw-r--r-- | hw/nx.c | 105 |
5 files changed, 596 insertions, 100 deletions
diff --git a/hw/Makefile.inc b/hw/Makefile.inc index 83125be..416d23c 100644 --- a/hw/Makefile.inc +++ b/hw/Makefile.inc @@ -2,7 +2,8 @@ SUBDIRS += hw HW_OBJS = xscom.o chiptod.o gx.o cec.o lpc.o lpc-uart.o psi.o -HW_OBJS += homer.o slw.o occ.o nx.o fsi-master.o centaur.o +HW_OBJS += homer.o slw.o occ.o fsi-master.o centaur.o +HW_OBJS += nx.o nx-rng.o nx-crypto.o nx-842.o HW_OBJS += p7ioc.o p7ioc-inits.o p7ioc-phb.o p5ioc2.o p5ioc2-phb.o HW_OBJS += phb3.o sfc-ctrl.o fake-rtc.o bt.o p8-i2c.o HW=hw/built-in.o diff --git a/hw/nx-842.c b/hw/nx-842.c new file mode 100644 index 0000000..b2ae425 --- /dev/null +++ b/hw/nx-842.c @@ -0,0 +1,212 @@ +/* Copyright 2015 IBM Corp. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + * implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include <skiboot.h> +#include <xscom.h> +#include <io.h> +#include <cpu.h> +#include <nx.h> + +/* Configuration settings */ +#define CFG_842_FC_ENABLE (0x1f) /* enable all 842 functions */ +#define CFG_842_ENABLE (1) /* enable 842 engines */ +#define DMA_COMPRESS_PREFETCH (1) /* enable prefetching */ +#define DMA_DECOMPRESS_PREFETCH (1) /* enable prefetching */ +#define DMA_COMPRESS_MAX_RR (15) /* range 1-15 */ +#define DMA_DECOMPRESS_MAX_RR (15) /* range 1-15 */ +#define DMA_SPBC (1) /* write SPBC in CPB */ +#define DMA_CSB_WR NX_DMA_CSB_WR_CI +#define DMA_COMPLETION_MODE NX_DMA_COMPLETION_MODE_CI +#define DMA_CPB_WR NX_DMA_CPB_WR_CI_PAD +#define DMA_OUTPUT_DATA_WR NX_DMA_OUTPUT_DATA_WR_CI +#define EE_0 (1) /* enable engine 0 */ +#define EE_1 (1) /* enable engine 1 */ + +/* counter used to provide unique Coprocessor Instance number */ +static u64 nx_842_ci_counter = 1; + +static int nx_cfg_842(u32 gcid, u64 xcfg, u64 instance) +{ + u64 cfg, ci, ct; + int rc; + + if (instance > NX_P8_842_CFG_CI_MAX) { + prerror("NX%d: ERROR: 842 CI %u exceeds max %u\n", + gcid, (unsigned int)instance, NX_P8_842_CFG_CI_MAX); + return OPAL_INTERNAL_ERROR; + } + + rc = xscom_read(gcid, xcfg, &cfg); + if (rc) + return rc; + + ct = GETFIELD(NX_P8_842_CFG_CT, cfg); + if (!ct) + prlog(PR_INFO, "NX%d: 842 CT set to %u\n", gcid, NX_CT_842); + else if (ct == NX_CT_842) + prlog(PR_INFO, "NX%d: 842 CT already set to %u\n", + gcid, NX_CT_842); + else + prlog(PR_INFO, "NX%d: 842 CT already set to %u, " + "changing to %u\n", gcid, (unsigned int)ct, NX_CT_842); + ct = NX_CT_842; + cfg = SETFIELD(NX_P8_842_CFG_CT, cfg, ct); + + /* Coprocessor Instance must be shifted left. + * See hw doc Section 5.5.1. + */ + ci = GETFIELD(NX_P8_842_CFG_CI, cfg) >> NX_P8_842_CFG_CI_LSHIFT; + if (!ci) + prlog(PR_INFO, "NX%d: 842 CI set to %u\n", gcid, + (unsigned int)instance); + else if (ci == instance) + prlog(PR_INFO, "NX%d: 842 CI already set to %u\n", gcid, + (unsigned int)instance); + else + prlog(PR_INFO, "NX%d: 842 CI already set to %u, " + "changing to %u\n", gcid, + (unsigned int)ci, (unsigned int)instance); + ci = instance; + cfg = SETFIELD(NX_P8_842_CFG_CI, cfg, ci << NX_P8_842_CFG_CI_LSHIFT); + + /* Enable all functions */ + cfg = SETFIELD(NX_P8_842_CFG_FC_ENABLE, cfg, CFG_842_FC_ENABLE); + + cfg = SETFIELD(NX_P8_842_CFG_ENABLE, cfg, CFG_842_ENABLE); + + rc = xscom_write(gcid, xcfg, cfg); + if (rc) + prerror("NX%d: ERROR: 842 CT %u CI %u config failure %d\n", + gcid, (unsigned int)ct, (unsigned int)ci, rc); + else + prlog(PR_DEBUG, "NX%d: 842 Config 0x%016lx\n", + gcid, (unsigned long)cfg); + + return rc; +} + +static int nx_cfg_dma(u32 gcid, u64 xcfg) +{ + u64 cfg; + int rc; + + rc = xscom_read(gcid, xcfg, &cfg); + if (rc) + return rc; + + cfg = SETFIELD(NX_P8_DMA_CFG_842_COMPRESS_PREFETCH, cfg, + DMA_COMPRESS_PREFETCH); + cfg = SETFIELD(NX_P8_DMA_CFG_842_DECOMPRESS_PREFETCH, cfg, + DMA_DECOMPRESS_PREFETCH); + cfg = SETFIELD(NX_P8_DMA_CFG_842_COMPRESS_MAX_RR, cfg, + DMA_COMPRESS_MAX_RR); + cfg = SETFIELD(NX_P8_DMA_CFG_842_DECOMPRESS_MAX_RR, cfg, + DMA_DECOMPRESS_MAX_RR); + cfg = SETFIELD(NX_P8_DMA_CFG_842_SPBC, cfg, + DMA_SPBC); + cfg = SETFIELD(NX_P8_DMA_CFG_842_CSB_WR, cfg, + DMA_CSB_WR); + cfg = SETFIELD(NX_P8_DMA_CFG_842_COMPLETION_MODE, cfg, + DMA_COMPLETION_MODE); + cfg = SETFIELD(NX_P8_DMA_CFG_842_CPB_WR, cfg, + DMA_CPB_WR); + cfg = SETFIELD(NX_P8_DMA_CFG_842_OUTPUT_DATA_WR, cfg, + DMA_OUTPUT_DATA_WR); + + rc = xscom_write(gcid, xcfg, cfg); + if (rc) + prerror("NX%d: ERROR: DMA config failure %d\n", gcid, rc); + else + prlog(PR_DEBUG, "NX%d: DMA 0x%016lx\n", gcid, + (unsigned long)cfg); + + return rc; +} + +static int nx_cfg_ee(u32 gcid, u64 xcfg) +{ + u64 cfg; + int rc; + + rc = xscom_read(gcid, xcfg, &cfg); + if (rc) + return rc; + + cfg = SETFIELD(NX_P8_EE_CFG_842_0, cfg, EE_0); + cfg = SETFIELD(NX_P8_EE_CFG_842_1, cfg, EE_1); + + rc = xscom_write(gcid, xcfg, cfg); + if (rc) + prerror("NX%d: ERROR: Engine Enable failure %d\n", gcid, rc); + else + prlog(PR_DEBUG, "NX%d: Engine Enable 0x%016lx\n", + gcid, (unsigned long)cfg); + + return rc; +} + +void nx_create_842_node(struct dt_node *node) +{ + u32 gcid; + u32 pb_base; + u64 cfg_dma, cfg_842, cfg_ee; + u64 instance; + struct dt_node *dt_842; + int rc; + char node_name[32]; + + gcid = dt_get_chip_id(node); + pb_base = dt_get_address(node, 0, NULL); + + prlog(PR_INFO, "NX%d: 842 at 0x%x\n", gcid, pb_base); + + if (dt_node_is_compatible(node, "ibm,power7-nx")) { + prerror("NX%d: ERROR: 842 not supported on Power7\n", gcid); + return; + } else if (dt_node_is_compatible(node, "ibm,power8-nx")) { + cfg_dma = pb_base + NX_P8_DMA_CFG; + cfg_842 = pb_base + NX_P8_842_CFG; + cfg_ee = pb_base + NX_P8_EE_CFG; + } else { + prerror("NX%d: ERROR: Unknown NX type!\n", gcid); + return; + } + + rc = nx_cfg_dma(gcid, cfg_dma); + if (rc) + return; + + instance = nx_842_ci_counter++; + rc = nx_cfg_842(gcid, cfg_842, instance); + if (rc) + return; + + rc = nx_cfg_ee(gcid, cfg_ee); + if (rc) + return; + + prlog(PR_INFO, "NX%d: 842 Coprocessor Enabled\n", gcid); + + snprintf(node_name, sizeof(node_name), "ibm,nx842-powernv#%d", gcid); + dt_842 = dt_new(dt_root, node_name); + if (!dt_842) + return; + + dt_add_property_strings(dt_842, "compatible", "ibm,nx842-powernv"); + dt_add_property_cells(dt_842, "ibm,chip-id", gcid); + dt_add_property_cells(dt_842, "ibm,coprocessor-type", NX_CT_842); + dt_add_property_cells(dt_842, "ibm,coprocessor-instance", instance); +} diff --git a/hw/nx-crypto.c b/hw/nx-crypto.c new file mode 100644 index 0000000..623ab84 --- /dev/null +++ b/hw/nx-crypto.c @@ -0,0 +1,277 @@ +/* Copyright 2015 IBM Corp. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + * implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include <skiboot.h> +#include <xscom.h> +#include <io.h> +#include <cpu.h> +#include <nx.h> + +/* Configuration settings */ +#define CFG_SYM_FC_ENABLE (0) /* disable all sym functions */ +#define CFG_SYM_ENABLE (0) /* disable sym engines */ +#define CFG_ASYM_FC_ENABLE (0) /* disable all asym functions */ +#define CFG_ASYM_ENABLE (0) /* disable asym engines */ +#define AES_SHA_MAX_RR (1) /* valid range: 1-8 */ +#define AES_SHA_CSB_WR NX_DMA_CSB_WR_PDMA +#define AES_SHA_COMPLETION_MODE NX_DMA_COMPLETION_MODE_PDMA +#define AES_SHA_CPB_WR NX_DMA_CPB_WR_DMA_NOPAD +#define AES_SHA_OUTPUT_DATA_WR NX_DMA_OUTPUT_DATA_WR_DMA +#define AMF_MAX_RR (1) /* valid range: 1-8 */ +#define AMF_CSB_WR NX_DMA_CSB_WR_PDMA +#define AMF_COMPLETION_MODE NX_DMA_COMPLETION_MODE_PDMA +#define AMF_CPB_WR (0) /* CPB WR not done with AMF */ +#define AMF_OUTPUT_DATA_WR NX_DMA_OUTPUT_DATA_WR_DMA +#define EE_AMF_0 (0) /* disable AMF engine 0 */ +#define EE_AMF_1 (0) /* disable AMF engine 1 */ +#define EE_AMF_2 (0) /* disable AMF engine 2 */ +#define EE_AMF_3 (0) /* disable AMF engine 3 */ +#define EE_SYM_0 (0) /* disable SYM engine 0 */ +#define EE_SYM_1 (0) /* disable SYM engine 1 */ + +/* counters used to provide unique Coprocessor Instance numbers */ +static u64 nx_sym_ci_counter = 1; +static u64 nx_asym_ci_counter = 1; + +static int nx_cfg_sym(u32 gcid, u64 xcfg, u64 instance) +{ + u64 cfg, ci, ct; + int rc; + + if (instance > NX_P8_SYM_CFG_CI_MAX) { + prerror("NX%d: ERROR: SYM CI %u exceeds max %u\n", + gcid, (unsigned int)instance, NX_P8_SYM_CFG_CI_MAX); + return OPAL_INTERNAL_ERROR; + } + + rc = xscom_read(gcid, xcfg, &cfg); + if (rc) + return rc; + + ct = GETFIELD(NX_P8_SYM_CFG_CT, cfg); + if (!ct) + prlog(PR_INFO, "NX%d: SYM CT set to %u\n", gcid, NX_CT_SYM); + else if (ct == NX_CT_SYM) + prlog(PR_INFO, "NX%d: SYM CT already set to %u\n", + gcid, NX_CT_SYM); + else + prlog(PR_INFO, "NX%d: SYM CT already set to %u, " + "changing to %u\n", gcid, (unsigned int)ct, NX_CT_SYM); + ct = NX_CT_SYM; + cfg = SETFIELD(NX_P8_SYM_CFG_CT, cfg, ct); + + /* Coprocessor Instance must be shifted left. + * See hw doc Section 5.5.1. + */ + ci = GETFIELD(NX_P8_SYM_CFG_CI, cfg) >> NX_P8_SYM_CFG_CI_LSHIFT; + if (!ci) + prlog(PR_INFO, "NX%d: SYM CI set to %u\n", gcid, + (unsigned int)instance); + else if (ci == instance) + prlog(PR_INFO, "NX%d: SYM CI already set to %u\n", gcid, + (unsigned int)instance); + else + prlog(PR_INFO, "NX%d: SYM CI already set to %u, " + "changing to %u\n", gcid, + (unsigned int)ci, (unsigned int)instance); + ci = instance; + cfg = SETFIELD(NX_P8_SYM_CFG_CI, cfg, ci << NX_P8_SYM_CFG_CI_LSHIFT); + + cfg = SETFIELD(NX_P8_SYM_CFG_FC_ENABLE, cfg, CFG_SYM_FC_ENABLE); + + cfg = SETFIELD(NX_P8_SYM_CFG_ENABLE, cfg, CFG_SYM_ENABLE); + + rc = xscom_write(gcid, xcfg, cfg); + if (rc) + prerror("NX%d: ERROR: SYM CT %u CI %u config failure %d\n", + gcid, (unsigned int)ct, (unsigned int)ci, rc); + else + prlog(PR_DEBUG, "NX%d: SYM Config 0x%016lx\n", + gcid, (unsigned long)cfg); + + return rc; +} + +static int nx_cfg_asym(u32 gcid, u64 xcfg, u64 instance) +{ + u64 cfg, ci, ct; + int rc; + + if (instance > NX_P8_ASYM_CFG_CI_MAX) { + prerror("NX%d: ERROR: ASYM CI %u exceeds max %u\n", + gcid, (unsigned int)instance, NX_P8_ASYM_CFG_CI_MAX); + return OPAL_INTERNAL_ERROR; + } + + rc = xscom_read(gcid, xcfg, &cfg); + if (rc) + return rc; + + ct = GETFIELD(NX_P8_ASYM_CFG_CT, cfg); + if (!ct) + prlog(PR_INFO, "NX%d: ASYM CT set to %u\n", + gcid, NX_CT_ASYM); + else if (ct == NX_CT_ASYM) + prlog(PR_INFO, "NX%d: ASYM CT already set to %u\n", + gcid, NX_CT_ASYM); + else + prlog(PR_INFO, "NX%d: ASYM CT already set to %u, " + "changing to %u\n", gcid, (unsigned int)ct, NX_CT_ASYM); + ct = NX_CT_ASYM; + cfg = SETFIELD(NX_P8_ASYM_CFG_CT, cfg, ct); + + /* Coprocessor Instance must be shifted left. + * See hw doc Section 5.5.1. + */ + ci = GETFIELD(NX_P8_ASYM_CFG_CI, cfg) >> NX_P8_ASYM_CFG_CI_LSHIFT; + if (!ci) + prlog(PR_INFO, "NX%d: ASYM CI set to %u\n", gcid, + (unsigned int)instance); + else if (ci == instance) + prlog(PR_INFO, "NX%d: ASYM CI already set to %u\n", gcid, + (unsigned int)instance); + else + prlog(PR_INFO, "NX%d: ASYM CI already set to %u, " + "changing to %u\n", gcid, + (unsigned int)ci, (unsigned int)instance); + ci = instance; + cfg = SETFIELD(NX_P8_ASYM_CFG_CI, cfg, ci << NX_P8_ASYM_CFG_CI_LSHIFT); + + cfg = SETFIELD(NX_P8_ASYM_CFG_FC_ENABLE, cfg, CFG_ASYM_FC_ENABLE); + + cfg = SETFIELD(NX_P8_ASYM_CFG_ENABLE, cfg, CFG_ASYM_ENABLE); + + rc = xscom_write(gcid, xcfg, cfg); + if (rc) + prerror("NX%d: ERROR: ASYM CT %u CI %u config failure %d\n", + gcid, (unsigned int)ct, (unsigned int)ci, rc); + else + prlog(PR_DEBUG, "NX%d: ASYM Config 0x%016lx\n", + gcid, (unsigned long)cfg); + + return rc; +} + +static int nx_cfg_dma(u32 gcid, u64 xcfg) +{ + u64 cfg; + int rc; + + rc = xscom_read(gcid, xcfg, &cfg); + if (rc) + return rc; + + cfg = SETFIELD(NX_P8_DMA_CFG_AES_SHA_MAX_RR, cfg, + AES_SHA_MAX_RR); + cfg = SETFIELD(NX_P8_DMA_CFG_AES_SHA_CSB_WR, cfg, + AES_SHA_CSB_WR); + cfg = SETFIELD(NX_P8_DMA_CFG_AES_SHA_COMPLETION_MODE, cfg, + AES_SHA_COMPLETION_MODE); + cfg = SETFIELD(NX_P8_DMA_CFG_AES_SHA_CPB_WR, cfg, + AES_SHA_CPB_WR); + cfg = SETFIELD(NX_P8_DMA_CFG_AES_SHA_OUTPUT_DATA_WR, cfg, + AES_SHA_OUTPUT_DATA_WR); + + cfg = SETFIELD(NX_P8_DMA_CFG_AMF_MAX_RR, cfg, + AMF_MAX_RR); + cfg = SETFIELD(NX_P8_DMA_CFG_AMF_CSB_WR, cfg, + AMF_CSB_WR); + cfg = SETFIELD(NX_P8_DMA_CFG_AMF_COMPLETION_MODE, cfg, + AMF_COMPLETION_MODE); + cfg = SETFIELD(NX_P8_DMA_CFG_AMF_CPB_WR, cfg, + AMF_CPB_WR); + cfg = SETFIELD(NX_P8_DMA_CFG_AMF_OUTPUT_DATA_WR, cfg, + AMF_OUTPUT_DATA_WR); + + rc = xscom_write(gcid, xcfg, cfg); + if (rc) + prerror("NX%d: ERROR: DMA config failure %d\n", gcid, rc); + else + prlog(PR_DEBUG, "NX%d: DMA 0x%016lx\n", gcid, + (unsigned long)cfg); + + return rc; +} + +static int nx_cfg_ee(u32 gcid, u64 xcfg) +{ + u64 cfg; + int rc; + + rc = xscom_read(gcid, xcfg, &cfg); + if (rc) + return rc; + + cfg = SETFIELD(NX_P8_EE_CFG_AMF_0, cfg, EE_AMF_0); + cfg = SETFIELD(NX_P8_EE_CFG_AMF_1, cfg, EE_AMF_1); + cfg = SETFIELD(NX_P8_EE_CFG_AMF_2, cfg, EE_AMF_2); + cfg = SETFIELD(NX_P8_EE_CFG_AMF_3, cfg, EE_AMF_3); + cfg = SETFIELD(NX_P8_EE_CFG_SYM_0, cfg, EE_SYM_0); + cfg = SETFIELD(NX_P8_EE_CFG_SYM_1, cfg, EE_SYM_1); + + rc = xscom_write(gcid, xcfg, cfg); + if (rc) + prerror("NX%d: ERROR: Engine Enable failure %d\n", gcid, rc); + else + prlog(PR_DEBUG, "NX%d: Engine Enable 0x%016lx\n", + gcid, (unsigned long)cfg); + + return rc; +} + +void nx_create_crypto_node(struct dt_node *node) +{ + u32 gcid; + u32 pb_base; + u64 cfg_dma, cfg_sym, cfg_asym, cfg_ee; + int rc; + + gcid = dt_get_chip_id(node); + pb_base = dt_get_address(node, 0, NULL); + + prlog(PR_INFO, "NX%d: Crypto at 0x%x\n", gcid, pb_base); + + if (dt_node_is_compatible(node, "ibm,power7-nx")) { + prerror("NX%d: ERROR: Crypto not supported on Power7\n", gcid); + return; + } else if (dt_node_is_compatible(node, "ibm,power8-nx")) { + cfg_dma = pb_base + NX_P8_DMA_CFG; + cfg_sym = pb_base + NX_P8_SYM_CFG; + cfg_asym = pb_base + NX_P8_ASYM_CFG; + cfg_ee = pb_base + NX_P8_EE_CFG; + } else { + prerror("NX%d: ERROR: Unknown NX type!\n", gcid); + return; + } + + rc = nx_cfg_dma(gcid, cfg_dma); + if (rc) + return; + + rc = nx_cfg_sym(gcid, cfg_sym, nx_sym_ci_counter++); + if (rc) + return; + + rc = nx_cfg_asym(gcid, cfg_asym, nx_asym_ci_counter++); + if (rc) + return; + + rc = nx_cfg_ee(gcid, cfg_ee); + if (rc) + return; + + prlog(PR_INFO, "NX%d: Crypto Coprocessors Disabled (not supported)\n", gcid); +} diff --git a/hw/nx-rng.c b/hw/nx-rng.c new file mode 100644 index 0000000..9cc5317 --- /dev/null +++ b/hw/nx-rng.c @@ -0,0 +1,99 @@ +/* Copyright 2013-2015 IBM Corp. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + * implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + + +#include <skiboot.h> +#include <xscom.h> +#include <io.h> +#include <cpu.h> +#include <nx.h> + +void nx_create_rng_node(struct dt_node *node) +{ + u64 bar, cfg; + u64 xbar, xcfg; + u32 pb_base; + u32 gcid; + u64 rng_addr, rng_len, len; + struct dt_node *rng; + int rc; + + gcid = dt_get_chip_id(node); + pb_base = dt_get_address(node, 0, NULL); + + if (dt_node_is_compatible(node, "ibm,power7-nx")) { + xbar = pb_base + NX_P7_RNG_BAR; + xcfg = pb_base + NX_P7_RNG_CFG; + } else if (dt_node_is_compatible(node, "ibm,power8-nx")) { + xbar = pb_base + NX_P8_RNG_BAR; + xcfg = pb_base + NX_P8_RNG_CFG; + } else { + prerror("NX%d: Unknown NX type!\n", gcid); + return; + } + + rc = xscom_read(gcid, xbar, &bar); /* Get RNG BAR */ + if (rc) + return; /* Hope xscom always prints error message */ + + rc = xscom_read(gcid, xcfg, &cfg); /* Get RNG CFG */ + if (rc) + return; + + /* + * We use the P8 BAR constants. The layout of the BAR is the + * same, with more bits at the top of P8 which are hard wired to + * 0 on P7. We also mask in-place rather than using GETFIELD + * for the base address as we happen to *know* that it's properly + * aligned in the register. + * + * FIXME? Always assusme BAR gets a valid address from FSP + */ + rng_addr = bar & NX_P8_RNG_BAR_ADDR; + len = GETFIELD(NX_P8_RNG_BAR_SIZE, bar); + if (len > 4) { + prerror("NX%d: Corrupted bar size %lld\n", gcid, len); + return; + } + rng_len = (u64[]){ 0x1000, /* 4K */ + 0x10000, /* 64K */ + 0x400000000, /* 16G*/ + 0x100000, /* 1M */ + 0x1000000 /* 16M */} [len]; + + + prlog(PR_INFO, "NX%d: RNG BAR set to 0x%016llx..0x%016llx\n", + gcid, rng_addr, rng_addr + rng_len - 1); + + /* RNG must be enabled before MMIO is enabled */ + rc = xscom_write(gcid, xcfg, cfg | NX_P8_RNG_CFG_ENABLE); + if (rc) + return; + + /* The BAR needs to be enabled too */ + rc = xscom_write(gcid, xbar, bar | NX_P8_RNG_BAR_ENABLE); + if (rc) + return; + rng = dt_new_addr(dt_root, "hwrng", rng_addr); + if (!rng) + return; + + dt_add_property_strings(rng, "compatible", "ibm,power-rng"); + dt_add_property_cells(rng, "reg", hi32(rng_addr), lo32(rng_addr), + hi32(rng_len), lo32(rng_len)); + dt_add_property_cells(rng, "ibm,chip-id", gcid); +} @@ -1,4 +1,4 @@ -/* Copyright 2013-2014 IBM Corp. +/* Copyright 2013-2015 IBM Corp. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -22,106 +22,13 @@ #include <cpu.h> #include <nx.h> -#define NX_P7_RNG_BAR XSCOM_SAT(0x1, 0x2, 0x0c) -#define NX_P7_RNG_BAR_ADDR_MASK PPC_BITMASK(18, 51) -#define NX_P7_RNG_BAR_ADDR_LSH PPC_BITLSHIFT(51) -#define NX_P7_RNG_BAR_SIZE_MASK PPC_BITMASK(53, 55) -#define NX_P7_RNG_BAR_SIZE_LSH PPC_BITLSHIFT(55) -#define NX_P7_RNG_BAR_ENABLE PPC_BIT(52) - -#define NX_P8_RNG_BAR XSCOM_SAT(0xc, 0x2, 0x0d) -#define NX_P8_RNG_BAR_ADDR_MASK PPC_BITMASK(14, 51) -#define NX_P8_RNG_BAR_ADDR_LSH PPC_BITLSHIFT(51) -#define NX_P8_RNG_BAR_SIZE_MASK PPC_BITMASK(53, 55) -#define NX_P8_RNG_BAR_SIZE_LSH PPC_BITLSHIFT(55) -#define NX_P8_RNG_BAR_ENABLE PPC_BIT(52) - -#define NX_P7_RNG_CFG XSCOM_SAT(0x1, 0x2, 0x12) -#define NX_P7_RNG_CFG_ENABLE PPC_BIT(63) -#define NX_P8_RNG_CFG XSCOM_SAT(0xc, 0x2, 0x12) -#define NX_P8_RNG_CFG_ENABLE PPC_BIT(63) - -static void nx_create_node(struct dt_node *node) -{ - u64 bar, cfg; - u64 xbar, xcfg; - u32 pb_base; - u32 gcid; - u64 rng_addr, rng_len, len; - struct dt_node *rng; - int rc; - - gcid = dt_get_chip_id(node); - pb_base = dt_get_address(node, 0, NULL); - - if (dt_node_is_compatible(node, "ibm,power7-nx")) { - xbar = pb_base + NX_P7_RNG_BAR; - xcfg = pb_base + NX_P7_RNG_CFG; - } else if (dt_node_is_compatible(node, "ibm,power8-nx")) { - xbar = pb_base + NX_P8_RNG_BAR; - xcfg = pb_base + NX_P8_RNG_CFG; - } else { - prerror("NX%d: Unknown NX type!\n", gcid); - return; - } - - rc = xscom_read(gcid, xbar, &bar); /* Get RNG BAR */ - if (rc) - return; /* Hope xscom always prints error message */ - - rc = xscom_read(gcid, xcfg, &cfg); /* Get RNG CFG */ - if (rc) - return; - - /* - * We use the P8 BAR constants. The layout of the BAR is the - * same, with more bits at the top of P8 which are hard wired to - * 0 on P7. We also mask in-place rather than using GETFIELD - * for the base address as we happen to *know* that it's properly - * aligned in the register. - * - * FIXME? Always assusme BAR gets a valid address from FSP - */ - rng_addr = bar & NX_P8_RNG_BAR_ADDR_MASK; - len = GETFIELD(NX_P8_RNG_BAR_SIZE, bar); - if (len > 4) { - prerror("NX%d: Corrupted bar size %lld\n", gcid, len); - return; - } - rng_len = (u64[]){ 0x1000, /* 4K */ - 0x10000, /* 64K */ - 0x400000000, /* 16G*/ - 0x100000, /* 1M */ - 0x1000000 /* 16M */} [len]; - - - printf("NX%d: RNG BAR set to 0x%016llx..0x%016llx\n", - gcid, rng_addr, rng_addr + rng_len - 1); - - /* RNG must be enabled before MMIO is enabled */ - rc = xscom_write(gcid, xcfg, cfg | NX_P8_RNG_CFG_ENABLE); - if (rc) - return; - - /* The BAR needs to be enabled too */ - rc = xscom_write(gcid, xbar, bar | NX_P8_RNG_BAR_ENABLE); - if (rc) - return; - rng = dt_new_addr(dt_root, "hwrng", rng_addr); - if (!rng) - return; - - dt_add_property_strings(rng, "compatible", "ibm,power-rng"); - dt_add_property_cells(rng, "reg", hi32(rng_addr), lo32(rng_addr), - hi32(rng_len), lo32(rng_len)); - dt_add_property_cells(rng, "ibm,chip-id", gcid); -} - -/* Create nodes for MMIO accesible components in NX (only RNG) */ void nx_init(void) { struct dt_node *node; - dt_for_each_compatible(dt_root, node, "ibm,power-nx") - nx_create_node(node); + dt_for_each_compatible(dt_root, node, "ibm,power-nx") { + nx_create_rng_node(node); + nx_create_crypto_node(node); + nx_create_842_node(node); + } } |