aboutsummaryrefslogtreecommitdiff
path: root/hw
diff options
context:
space:
mode:
Diffstat (limited to 'hw')
-rw-r--r--hw/npu.c1
-rw-r--r--hw/p7ioc-phb.c6
-rw-r--r--hw/phb3.c31
-rw-r--r--hw/phb4.c31
4 files changed, 30 insertions, 39 deletions
diff --git a/hw/npu.c b/hw/npu.c
index 685acc6..5232954 100644
--- a/hw/npu.c
+++ b/hw/npu.c
@@ -850,7 +850,6 @@ static struct pci_slot *npu_slot_create(struct phb *phb)
slot->ops.poll_link = NULL;
slot->ops.hreset = npu_hreset;
slot->ops.freset = npu_freset;
- slot->ops.pfreset = NULL;
slot->ops.creset = NULL;
return slot;
diff --git a/hw/p7ioc-phb.c b/hw/p7ioc-phb.c
index 1f1b362..50608e2 100644
--- a/hw/p7ioc-phb.c
+++ b/hw/p7ioc-phb.c
@@ -2228,11 +2228,6 @@ static int64_t p7ioc_freset(struct pci_slot *slot)
reg64 = in_be64(p->regs + PHB_RESET);
reg64 |= 0x2000000000000000ul;
out_be64(p->regs + PHB_RESET, reg64);
- if (slot->ops.pfreset) {
- pci_slot_set_state(slot,
- P7IOC_SLOT_PFRESET_START);
- return slot->ops.pfreset(slot);
- }
pci_slot_set_state(slot, P7IOC_SLOT_LINK_START);
return slot->ops.poll_link(slot);
@@ -2321,7 +2316,6 @@ static struct pci_slot *p7ioc_phb_slot_create(struct phb *phb)
slot->ops.poll_link = p7ioc_poll_link;
slot->ops.hreset = p7ioc_hreset;
slot->ops.freset = p7ioc_freset;
- slot->ops.pfreset = NULL;
slot->ops.creset = p7ioc_creset;
return slot;
diff --git a/hw/phb3.c b/hw/phb3.c
index 1c09ffe..52b30c2 100644
--- a/hw/phb3.c
+++ b/hw/phb3.c
@@ -2261,7 +2261,7 @@ static int64_t phb3_hreset(struct pci_slot *slot)
return OPAL_HARDWARE;
}
-static int64_t phb3_pfreset(struct pci_slot *slot)
+static int64_t phb3_freset(struct pci_slot *slot)
{
struct phb3 *p = phb_to_phb3(slot->phb);
uint8_t presence = 1;
@@ -2269,48 +2269,48 @@ static int64_t phb3_pfreset(struct pci_slot *slot)
switch(slot->state) {
case PHB3_SLOT_NORMAL:
- PHBDBG(p, "PFRESET: Starts\n");
+ PHBDBG(p, "FRESET: Starts\n");
/* Nothing to do without adapter connected */
if (slot->ops.get_presence_state)
slot->ops.get_presence_state(slot, &presence);
if (!presence) {
- PHBDBG(p, "PFRESET: No device\n");
+ PHBDBG(p, "FRESET: No device\n");
return OPAL_SUCCESS;
}
- PHBDBG(p, "PFRESET: Prepare for link down\n");
- slot->retry_state = PHB3_SLOT_PFRESET_START;
+ PHBDBG(p, "FRESET: Prepare for link down\n");
+ slot->retry_state = PHB3_SLOT_FRESET_START;
if (slot->ops.prepare_link_change)
slot->ops.prepare_link_change(slot, false);
/* fall through */
- case PHB3_SLOT_PFRESET_START:
+ case PHB3_SLOT_FRESET_START:
if (!p->skip_perst) {
- PHBDBG(p, "PFRESET: Assert\n");
+ PHBDBG(p, "FRESET: Assert\n");
reg = in_be64(p->regs + PHB_RESET);
reg &= ~0x2000000000000000ul;
out_be64(p->regs + PHB_RESET, reg);
pci_slot_set_state(slot,
- PHB3_SLOT_PFRESET_ASSERT_DELAY);
+ PHB3_SLOT_FRESET_ASSERT_DELAY);
return pci_slot_set_sm_timeout(slot, secs_to_tb(1));
}
/* To skip the assert during boot time */
- PHBDBG(p, "PFRESET: Assert skipped\n");
- pci_slot_set_state(slot, PHB3_SLOT_PFRESET_ASSERT_DELAY);
+ PHBDBG(p, "FRESET: Assert skipped\n");
+ pci_slot_set_state(slot, PHB3_SLOT_FRESET_ASSERT_DELAY);
p->skip_perst = false;
/* fall through */
- case PHB3_SLOT_PFRESET_ASSERT_DELAY:
- PHBDBG(p, "PFRESET: Deassert\n");
+ case PHB3_SLOT_FRESET_ASSERT_DELAY:
+ PHBDBG(p, "FRESET: Deassert\n");
reg = in_be64(p->regs + PHB_RESET);
reg |= 0x2000000000000000ul;
out_be64(p->regs + PHB_RESET, reg);
pci_slot_set_state(slot,
- PHB3_SLOT_PFRESET_DEASSERT_DELAY);
+ PHB3_SLOT_FRESET_DEASSERT_DELAY);
/* CAPP FPGA requires 1s to flash before polling link */
return pci_slot_set_sm_timeout(slot, secs_to_tb(1));
- case PHB3_SLOT_PFRESET_DEASSERT_DELAY:
+ case PHB3_SLOT_FRESET_DEASSERT_DELAY:
pci_slot_set_state(slot, PHB3_SLOT_LINK_START);
return slot->ops.poll_link(slot);
default:
@@ -2595,8 +2595,7 @@ static struct pci_slot *phb3_slot_create(struct phb *phb)
slot->ops.prepare_link_change = phb3_prepare_link_change;
slot->ops.poll_link = phb3_poll_link;
slot->ops.hreset = phb3_hreset;
- slot->ops.freset = phb3_pfreset;
- slot->ops.pfreset = phb3_pfreset;
+ slot->ops.freset = phb3_freset;
slot->ops.creset = phb3_creset;
return slot;
diff --git a/hw/phb4.c b/hw/phb4.c
index efb6a5f..a21aa1a 100644
--- a/hw/phb4.c
+++ b/hw/phb4.c
@@ -1901,7 +1901,7 @@ static int64_t phb4_hreset(struct pci_slot *slot)
return OPAL_HARDWARE;
}
-static int64_t phb4_pfreset(struct pci_slot *slot)
+static int64_t phb4_freset(struct pci_slot *slot)
{
struct phb4 *p = phb_to_phb4(slot->phb);
uint8_t presence = 1;
@@ -1909,48 +1909,48 @@ static int64_t phb4_pfreset(struct pci_slot *slot)
switch(slot->state) {
case PHB4_SLOT_NORMAL:
- PHBDBG(p, "PFRESET: Starts\n");
+ PHBDBG(p, "FRESET: Starts\n");
/* Nothing to do without adapter connected */
if (slot->ops.get_presence_state)
slot->ops.get_presence_state(slot, &presence);
if (!presence) {
- PHBDBG(p, "PFRESET: No device\n");
+ PHBDBG(p, "FRESET: No device\n");
return OPAL_SUCCESS;
}
- PHBDBG(p, "PFRESET: Prepare for link down\n");
- slot->retry_state = PHB4_SLOT_PFRESET_START;
+ PHBDBG(p, "FRESET: Prepare for link down\n");
+ slot->retry_state = PHB4_SLOT_FRESET_START;
if (slot->ops.prepare_link_change)
slot->ops.prepare_link_change(slot, false);
/* fall through */
- case PHB4_SLOT_PFRESET_START:
+ case PHB4_SLOT_FRESET_START:
if (!p->skip_perst) {
- PHBDBG(p, "PFRESET: Assert\n");
+ PHBDBG(p, "FRESET: Assert\n");
reg = in_be64(p->regs + PHB_PCIE_CRESET);
reg &= ~PHB_PCIE_CRESET_PERST_N;
out_be64(p->regs + PHB_PCIE_CRESET, reg);
pci_slot_set_state(slot,
- PHB4_SLOT_PFRESET_ASSERT_DELAY);
+ PHB4_SLOT_FRESET_ASSERT_DELAY);
return pci_slot_set_sm_timeout(slot, secs_to_tb(1));
}
/* To skip the assert during boot time */
- PHBDBG(p, "PFRESET: Assert skipped\n");
- pci_slot_set_state(slot, PHB4_SLOT_PFRESET_ASSERT_DELAY);
+ PHBDBG(p, "FRESET: Assert skipped\n");
+ pci_slot_set_state(slot, PHB4_SLOT_FRESET_ASSERT_DELAY);
p->skip_perst = false;
/* fall through */
- case PHB4_SLOT_PFRESET_ASSERT_DELAY:
- PHBDBG(p, "PFRESET: Deassert\n");
+ case PHB4_SLOT_FRESET_ASSERT_DELAY:
+ PHBDBG(p, "FRESET: Deassert\n");
reg = in_be64(p->regs + PHB_PCIE_CRESET);
reg |= PHB_PCIE_CRESET_PERST_N;
out_be64(p->regs + PHB_PCIE_CRESET, reg);
pci_slot_set_state(slot,
- PHB4_SLOT_PFRESET_DEASSERT_DELAY);
+ PHB4_SLOT_FRESET_DEASSERT_DELAY);
/* CAPP FPGA requires 1s to flash before polling link */
return pci_slot_set_sm_timeout(slot, secs_to_tb(1));
- case PHB4_SLOT_PFRESET_DEASSERT_DELAY:
+ case PHB4_SLOT_FRESET_DEASSERT_DELAY:
pci_slot_set_state(slot, PHB4_SLOT_LINK_START);
return slot->ops.poll_link(slot);
default:
@@ -2035,8 +2035,7 @@ static struct pci_slot *phb4_slot_create(struct phb *phb)
slot->ops.prepare_link_change = phb4_prepare_link_change;
slot->ops.poll_link = phb4_poll_link;
slot->ops.hreset = phb4_hreset;
- slot->ops.freset = phb4_pfreset;
- slot->ops.pfreset = phb4_pfreset;
+ slot->ops.freset = phb4_freset;
slot->ops.creset = phb4_creset;
return slot;
generated by cgit v1.1 at 2024-11-15 17:59:21 +0000