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-rw-r--r--doc/release-notes/skiboot-5.1.0-beta2.txt2
-rw-r--r--doc/release-notes/skiboot-5.1.0.txt2
-rw-r--r--doc/release-notes/skiboot-5.1.12.txt2
-rw-r--r--doc/release-notes/skiboot-5.1.2.txt2
-rw-r--r--doc/release-notes/skiboot-5.2.2.txt2
5 files changed, 5 insertions, 5 deletions
diff --git a/doc/release-notes/skiboot-5.1.0-beta2.txt b/doc/release-notes/skiboot-5.1.0-beta2.txt
index 3473d89..ebd7fc0 100644
--- a/doc/release-notes/skiboot-5.1.0-beta2.txt
+++ b/doc/release-notes/skiboot-5.1.0-beta2.txt
@@ -44,7 +44,7 @@ Over skiboot-5.1.0-beta1, the following bugs have been fixed:
to have shared mode. So we have to cut off the first M64 segment,
which corresponds to reserved PE#0 in kernel. If the first BAR
(for example PF's IOV BAR) requires huge alignment in kernel, we
- have to waste huge M64 space to accomodate the alignment. If we
+ have to waste huge M64 space to accommodate the alignment. If we
have reserved PE#256, the waste of M64 space will be avoided.
Other changes:
diff --git a/doc/release-notes/skiboot-5.1.0.txt b/doc/release-notes/skiboot-5.1.0.txt
index 127c975..8558378 100644
--- a/doc/release-notes/skiboot-5.1.0.txt
+++ b/doc/release-notes/skiboot-5.1.0.txt
@@ -104,7 +104,7 @@ The following bugs have been fixed:
to have shared mode. So we have to cut off the first M64 segment,
which corresponds to reserved PE#0 in kernel. If the first BAR
(for example PF's IOV BAR) requires huge alignment in kernel, we
- have to waste huge M64 space to accomodate the alignment. If we
+ have to waste huge M64 space to accommodate the alignment. If we
have reserved PE#256, the waste of M64 space will be avoided.
FSP-specific bugs fixed:
diff --git a/doc/release-notes/skiboot-5.1.12.txt b/doc/release-notes/skiboot-5.1.12.txt
index 6368473..49a7e25 100644
--- a/doc/release-notes/skiboot-5.1.12.txt
+++ b/doc/release-notes/skiboot-5.1.12.txt
@@ -25,7 +25,7 @@ POWER8 PHB (PCIe) specific:
- hw/phb3: Flush cache line after updating P/Q bits
When doing an MSI EOI, we update the P and Q bits in the IVE. That causes
the corresponding cache line to be dirty in the L3 which will cause a
- subsequent update by the PHB (upon recieving the next MSI) to get a few
+ subsequent update by the PHB (upon receiving the next MSI) to get a few
retries until it gets flushed.
We improve the situation (and thus performance) by doing a dcbf
diff --git a/doc/release-notes/skiboot-5.1.2.txt b/doc/release-notes/skiboot-5.1.2.txt
index 6e112a5..e64932e 100644
--- a/doc/release-notes/skiboot-5.1.2.txt
+++ b/doc/release-notes/skiboot-5.1.2.txt
@@ -31,7 +31,7 @@ Over skiboot-5.1.1, we have the following changes:
- build improvements
- fixes for two compiler warnings were squashed in 5.1.1 commit,
re-introduce the fixes.
- - misc complier/static analysis warning fixes
+ - misc compiler/static analysis warning fixes
- gard utility:
- If gard tool detects the GUARD PNOR partition is corrupted, it will
diff --git a/doc/release-notes/skiboot-5.2.2.txt b/doc/release-notes/skiboot-5.2.2.txt
index 603270c..3c65e11 100644
--- a/doc/release-notes/skiboot-5.2.2.txt
+++ b/doc/release-notes/skiboot-5.2.2.txt
@@ -9,7 +9,7 @@ first released August 17th, 2015.
Skiboot 5.2.2 replaces skiboot-5.2.1 as the current stable version, which was
released on April 27th, 2016. Over skiboot-5.2.1, skiboot 5.2.2 contains
-one bug fix targetted at P8NVL systems, notably the Garrison platform.
+one bug fix targeted at P8NVL systems, notably the Garrison platform.
skiboot-5.2.2 contains all bug fixes as of skiboot-5.1.16.