diff options
| -rw-r--r-- | asm/head.S | 10 | ||||
| -rw-r--r-- | core/affinity.c | 2 | ||||
| -rw-r--r-- | core/direct-controls.c | 13 | ||||
| -rw-r--r-- | core/fast-reboot.c | 6 | ||||
| -rw-r--r-- | core/pci.c | 43 | ||||
| -rw-r--r-- | hdata/Makefile.inc | 2 | ||||
| -rw-r--r-- | hdata/cpu-common.c | 4 | ||||
| -rw-r--r-- | hdata/hdata.h | 5 | ||||
| -rw-r--r-- | hdata/paca.c | 331 | ||||
| -rw-r--r-- | hdata/pcia.c | 5 | ||||
| -rw-r--r-- | hdata/spira.c | 11 | ||||
| -rw-r--r-- | hdata/spira.h | 118 | ||||
| -rw-r--r-- | hdata/test/hdata_to_dt.c | 3 | ||||
| -rw-r--r-- | hdata/vpd.c | 1 | ||||
| -rw-r--r-- | hw/fsp/fsp-console.c | 58 | ||||
| -rw-r--r-- | hw/fsp/fsp-occ.c | 4 | ||||
| -rw-r--r-- | hw/fsp/fsp-sysdump.c | 19 | ||||
| -rw-r--r-- | hw/fsp/fsp.c | 5 | ||||
| -rw-r--r-- | hw/npu.c | 1 | ||||
| -rw-r--r-- | hw/npu2-opencapi.c | 1 | ||||
| -rw-r--r-- | hw/npu2.c | 1 | ||||
| -rw-r--r-- | hw/nx-842.c | 11 | ||||
| -rw-r--r-- | hw/occ.c | 8 | ||||
| -rw-r--r-- | hw/phb3.c | 11 | ||||
| -rw-r--r-- | hw/phb4.c | 11 | ||||
| -rw-r--r-- | hw/psi.c | 3 | ||||
| -rw-r--r-- | hw/slw.c | 3 | ||||
| -rw-r--r-- | hw/xscom.c | 10 | ||||
| -rw-r--r-- | include/chip.h | 4 | ||||
| -rw-r--r-- | include/mem-map.h | 2 | ||||
| -rw-r--r-- | include/nx.h | 2 | ||||
| -rw-r--r-- | include/pci.h | 6 |
32 files changed, 81 insertions, 633 deletions
@@ -861,16 +861,6 @@ hv_lid_load_table: .long 0 - /* The FSP seems to ignore our primary/secondary entry - * points and instead copy that bit down to 0x180 and - * patch the first instruction to get our expected - * boot CPU number. We ignore that patching for now and - * got to the same entry we use for pHyp and FDT HB. - */ -opal_boot_trampoline: - li %r27,-1 - ba boot_entry - __head - /* * * OPAL entry point from operating system diff --git a/core/affinity.c b/core/affinity.c index d2bf030..dabe893 100644 --- a/core/affinity.c +++ b/core/affinity.c @@ -47,7 +47,7 @@ static uint32_t get_chip_node_id(struct proc_chip *chip) /* * Else use the 3 top bits of the chip ID which should be - * the node on both P7 and P8 + * the node on P8 */ return chip->id >> 3; } diff --git a/core/direct-controls.c b/core/direct-controls.c index 507a16f..793ef29 100644 --- a/core/direct-controls.c +++ b/core/direct-controls.c @@ -522,7 +522,7 @@ int dctl_set_special_wakeup(struct cpu_thread *t) struct cpu_thread *c = t->primary; int rc = OPAL_SUCCESS; - if (proc_gen != proc_gen_p9 && proc_gen != proc_gen_p8) + if (proc_gen == proc_gen_unknown) return OPAL_UNSUPPORTED; lock(&c->dctl_lock); @@ -544,7 +544,7 @@ int dctl_clear_special_wakeup(struct cpu_thread *t) struct cpu_thread *c = t->primary; int rc = OPAL_SUCCESS; - if (proc_gen != proc_gen_p9 && proc_gen != proc_gen_p8) + if (proc_gen == proc_gen_unknown) return OPAL_UNSUPPORTED; lock(&c->dctl_lock); @@ -592,9 +592,6 @@ static int dctl_stop(struct cpu_thread *t) struct cpu_thread *c = t->primary; int rc; - if (proc_gen != proc_gen_p9 && proc_gen != proc_gen_p8) - return OPAL_UNSUPPORTED; - lock(&c->dctl_lock); if (t->dctl_stopped) { unlock(&c->dctl_lock); @@ -643,9 +640,6 @@ static int dctl_sreset(struct cpu_thread *t) struct cpu_thread *c = t->primary; int rc; - if (proc_gen != proc_gen_p9 && proc_gen != proc_gen_p8) - return OPAL_UNSUPPORTED; - lock(&c->dctl_lock); if (!t->dctl_stopped) { unlock(&c->dctl_lock); @@ -669,6 +663,9 @@ int sreset_all_prepare(void) { struct cpu_thread *cpu; + if (proc_gen == proc_gen_unknown) + return OPAL_UNSUPPORTED; + prlog(PR_DEBUG, "RESET: Resetting from cpu: 0x%x (core 0x%x)\n", this_cpu()->pir, pir_to_core_id(this_cpu()->pir)); diff --git a/core/fast-reboot.c b/core/fast-reboot.c index 6de7b06..410acfe 100644 --- a/core/fast-reboot.c +++ b/core/fast-reboot.c @@ -103,12 +103,6 @@ void fast_reboot(void) { static int fast_reboot_count = 0; - if (!chip_quirk(QUIRK_MAMBO_CALLOUTS) && - (proc_gen != proc_gen_p8 && proc_gen != proc_gen_p9)) { - prlog(PR_DEBUG, - "RESET: Fast reboot not available on this CPU\n"); - return; - } if (chip_quirk(QUIRK_NO_DIRECT_CTL)) { prlog(PR_DEBUG, "RESET: Fast reboot disabled by quirk\n"); @@ -736,9 +736,8 @@ uint8_t pci_scan_bus(struct phb *phb, uint8_t bus, uint8_t max_bus, bool scan_downstream) { struct pci_device *pd = NULL, *rc = NULL; - uint8_t dev, fn, next_bus, max_sub, save_max; + uint8_t dev, fn, next_bus, max_sub; uint32_t scan_map; - bool use_max; /* Decide what to scan */ scan_map = parent ? parent->scan_map : phb->scan_map; @@ -772,8 +771,7 @@ uint8_t pci_scan_bus(struct phb *phb, uint8_t bus, uint8_t max_bus, * if PCI hotplug is supported. */ if (rc && rc->slot && rc->slot->pluggable) { - next_bus = phb->ops->choose_bus(phb, rc, bus + 1, - &max_bus, &use_max); + next_bus = bus + 1; rc->secondary_bus = next_bus; rc->subordinate_bus = max_bus; pci_cfg_write8(phb, rc->bdfn, PCI_CFG_SECONDARY_BUS, @@ -803,7 +801,6 @@ uint8_t pci_scan_bus(struct phb *phb, uint8_t bus, uint8_t max_bus, next_bus = bus + 1; max_sub = bus; - save_max = max_bus; /* Scan down bridges */ list_for_each(list, pd, link) { @@ -812,33 +809,6 @@ uint8_t pci_scan_bus(struct phb *phb, uint8_t bus, uint8_t max_bus, if (!pd->is_bridge) continue; - /* We need to figure out a new bus number to start from. - * - * This can be tricky due to our HW constraints which differ - * from bridge to bridge so we are going to let the phb - * driver decide what to do. This can return us a maximum - * bus number to assign as well - * - * This function will: - * - * - Return the bus number to use as secondary for the - * bridge or 0 for a failure - * - * - "max_bus" will be adjusted to represent the max - * subordinate that can be associated with the downstream - * device - * - * - "use_max" will be set to true if the returned max_bus - * *must* be used as the subordinate bus number of that - * bridge (when we need to give aligned powers of two's - * on P7IOC). If is is set to false, we just adjust the - * subordinate bus number based on what we probed. - * - */ - max_bus = save_max; - next_bus = phb->ops->choose_bus(phb, pd, next_bus, - &max_bus, &use_max); - /* Configure the bridge with the returned values */ if (next_bus <= bus) { PCIERR(phb, pd->bdfn, "Out of bus numbers !\n"); @@ -852,8 +822,8 @@ uint8_t pci_scan_bus(struct phb *phb, uint8_t bus, uint8_t max_bus, if (!next_bus) break; - PCIDBG(phb, pd->bdfn, "Bus %02x..%02x %s scanning...\n", - next_bus, max_bus, use_max ? "[use max]" : ""); + PCIDBG(phb, pd->bdfn, "Bus %02x..%02x scanning...\n", + next_bus, max_bus); /* Clear up bridge resources */ pci_cleanup_bridge(phb, pd); @@ -869,7 +839,7 @@ uint8_t pci_scan_bus(struct phb *phb, uint8_t bus, uint8_t max_bus, if (do_scan) { max_sub = pci_scan_bus(phb, next_bus, max_bus, &pd->children, pd, true); - } else if (!use_max) { + } else { /* Empty bridge. We leave room for hotplug * slots if the downstream port is pluggable. */ @@ -882,9 +852,6 @@ uint8_t pci_scan_bus(struct phb *phb, uint8_t bus, uint8_t max_bus, } } - /* Update the max subordinate as described previously */ - if (use_max) - max_sub = max_bus; pd->subordinate_bus = max_sub; pci_cfg_write8(phb, pd->bdfn, PCI_CFG_SUBORDINATE_BUS, max_sub); next_bus = max_sub + 1; diff --git a/hdata/Makefile.inc b/hdata/Makefile.inc index 6f47314..2d52f76 100644 --- a/hdata/Makefile.inc +++ b/hdata/Makefile.inc @@ -1,7 +1,7 @@ # -*-Makefile-*- SUBDIRS += hdata -HDATA_OBJS = spira.o paca.o pcia.o hdif.o memory.o fsp.o iohub.o vpd.o slca.o +HDATA_OBJS = spira.o pcia.o hdif.o memory.o fsp.o iohub.o vpd.o slca.o HDATA_OBJS += cpu-common.o vpd-common.o hostservices.o i2c.o tpmrel.o DEVSRC_OBJ = hdata/built-in.a diff --git a/hdata/cpu-common.c b/hdata/cpu-common.c index 55a663f..b229f64 100644 --- a/hdata/cpu-common.c +++ b/hdata/cpu-common.c @@ -11,7 +11,7 @@ struct dt_node * add_core_common(struct dt_node *cpus, const struct sppcia_cpu_cache *cache, - const struct sppaca_cpu_timebase *tb, + const struct sppcia_cpu_timebase *tb, uint32_t int_server, bool okay) { const char *name; @@ -107,7 +107,7 @@ struct dt_node * add_core_common(struct dt_node *cpus, dt_add_property_cells(cpu, "ibm,processor-radix-AP-encodings", 0x0000000c, 0xa0000010, 0x20000015, 0x4000001e); - /* Page size encodings appear to be the same for P7 and P8 */ + /* HPT segment page size encodings, common to all supported CPUs */ dt_add_property_cells(cpu, "ibm,segment-page-sizes", 0x0c, 0x000, 3, 0x0c, 0x0000, /* 4K seg 4k pages */ 0x10, 0x0007, /* 4K seg 64k pages */ diff --git a/hdata/hdata.h b/hdata/hdata.h index f778471..7504b1e 100644 --- a/hdata/hdata.h +++ b/hdata/hdata.h @@ -9,7 +9,6 @@ struct dt_node; extern void memory_parse(void); -extern int paca_parse(void); extern bool pcia_parse(void); extern void fsp_parse(void); extern void bmc_parse(void); @@ -25,8 +24,8 @@ extern struct dt_node *find_xscom_for_chip(uint32_t chip_id); extern uint32_t pcid_to_chip_id(uint32_t proc_chip_id); extern struct dt_node *add_core_common(struct dt_node *cpus, - const struct sppaca_cpu_cache *cache, - const struct sppaca_cpu_timebase *tb, + const struct sppcia_cpu_cache *cache, + const struct sppcia_cpu_timebase *tb, uint32_t int_server, bool okay); extern void add_core_attr(struct dt_node *cpu, uint32_t attr); extern uint32_t add_core_cache_info(struct dt_node *cpus, diff --git a/hdata/paca.c b/hdata/paca.c deleted file mode 100644 index 28025b0..0000000 --- a/hdata/paca.c +++ /dev/null @@ -1,331 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 -/* Copyright 2013-2017 IBM Corp. */ - -#include <skiboot.h> -#include "spira.h" -#include <cpu.h> -#include <fsp.h> -#include <opal.h> -#include <ccan/str/str.h> -#include <device.h> -#include <types.h> - -#include "hdata.h" - -#define PACA_MAX_THREADS 4 - -static unsigned int paca_index(const struct HDIF_common_hdr *paca) -{ - void *start = get_hdif(&spira.ntuples.paca, PACA_HDIF_SIG); - return ((void *)paca - start) - / be32_to_cpu(spira.ntuples.paca.alloc_len); -} - -static struct dt_node *add_cpu_node(struct dt_node *cpus, - const struct HDIF_common_hdr *paca, - const struct sppaca_cpu_id *id, - bool okay) -{ - const struct sppaca_cpu_timebase *timebase; - const struct sppaca_cpu_cache *cache; - const struct sppaca_cpu_attr *attr; - struct dt_node *cpu; - u32 no, size, ve_flags, l2_phandle, chip_id; - - /* We use the process_interrupt_line as the res id */ - no = be32_to_cpu(id->process_interrupt_line); - - ve_flags = be32_to_cpu(id->verify_exists_flags); - prlog(PR_INFO, "CPU[%i]: PIR=%i RES=%i %s %s(%u threads)\n", - paca_index(paca), be32_to_cpu(id->pir), no, - ve_flags & CPU_ID_PACA_RESERVED - ? "**RESERVED**" : cpu_state(ve_flags), - ve_flags & CPU_ID_SECONDARY_THREAD - ? "[secondary] " : - (be32_to_cpu(id->pir) == boot_cpu->pir ? "[boot] " : ""), - ((ve_flags & CPU_ID_NUM_SECONDARY_THREAD_MASK) - >> CPU_ID_NUM_SECONDARY_THREAD_SHIFT) + 1); - - timebase = HDIF_get_idata(paca, SPPACA_IDATA_TIMEBASE, &size); - if (!timebase || size < sizeof(*timebase)) { - prerror("CPU[%i]: bad timebase size %u @ %p\n", - paca_index(paca), size, timebase); - return NULL; - } - - cache = HDIF_get_idata(paca, SPPACA_IDATA_CACHE_SIZE, &size); - if (!cache || size < sizeof(*cache)) { - prerror("CPU[%i]: bad cache size %u @ %p\n", - paca_index(paca), size, cache); - return NULL; - } - - cpu = add_core_common(cpus, cache, timebase, no, okay); - - /* Core attributes */ - attr = HDIF_get_idata(paca, SPPACA_IDATA_CPU_ATTR, &size); - if (attr) - add_core_attr(cpu, be32_to_cpu(attr->attr)); - - /* Add cache info */ - l2_phandle = add_core_cache_info(cpus, cache, no, okay); - dt_add_property_cells(cpu, "l2-cache", l2_phandle); - - /* We append the secondary cpus in __cpu_parse */ - dt_add_property_cells(cpu, "ibm,ppc-interrupt-server#s", no); - - dt_add_property_cells(cpu, DT_PRIVATE "hw_proc_id", - be32_to_cpu(id->hardware_proc_id)); - dt_add_property_cells(cpu, "ibm,pir", be32_to_cpu(id->pir)); - - chip_id = pcid_to_chip_id(be32_to_cpu(id->processor_chip_id)); - dt_add_property_cells(cpu, "ibm,chip-id", chip_id); - - return cpu; -} - -static struct dt_node *find_cpu_by_hardware_proc_id(struct dt_node *root, - u32 hw_proc_id) -{ - struct dt_node *i; - - dt_for_each_node(root, i) { - const struct dt_property *prop; - - if (!dt_has_node_property(i, "device_type", "cpu")) - continue; - - prop = dt_find_property(i, DT_PRIVATE "hw_proc_id"); - if (!prop) - return NULL; - - if (be32_to_cpu(*(be32 *)prop->prop) == hw_proc_id) - return i; - } - return NULL; -} - -/* Note that numbers are small. */ -static void add_be32_sorted(__be32 arr[], __be32 new, unsigned num) -{ - unsigned int i; - - /* Walk until we find where we belong (insertion sort). */ - for (i = 0; i < num; i++) { - if (be32_to_cpu(new) < be32_to_cpu(arr[i])) { - __be32 tmp = arr[i]; - arr[i] = new; - new = tmp; - } - } - arr[i] = new; -} - -static void add_xics_icps(void) -{ - struct dt_node *cpu; - unsigned int i; - u64 reg[PACA_MAX_THREADS * 2]; - struct dt_node *icp; - - dt_for_each_node(dt_root, cpu) { - u32 irange[2], size, pir; - const struct dt_property *intsrv; - const struct HDIF_common_hdr *paca; - u64 ibase; - unsigned int num_threads; - bool found = false; - - if (!dt_has_node_property(cpu, "device_type", "cpu")) - continue; - - intsrv = dt_find_property(cpu, "ibm,ppc-interrupt-server#s"); - if (!intsrv) - continue; - - pir = dt_prop_get_u32(cpu, "ibm,pir"); - - /* Get ibase address */ - paca = get_hdif(&spira.ntuples.paca, PACA_HDIF_SIG); - for_each_paca(paca) { - const struct sppaca_cpu_id *id; - id = HDIF_get_idata(paca, SPPACA_IDATA_CPU_ID, &size); - - if (!CHECK_SPPTR(id)) - continue; - - if (pir != be32_to_cpu(id->pir)) - continue; - ibase = cleanup_addr(be64_to_cpu(id->ibase)); - found = true; - break; - } - if (!found) - return; - - num_threads = intsrv->len / sizeof(u32); - assert(num_threads <= PACA_MAX_THREADS); - - icp = dt_new_addr(dt_root, "interrupt-controller", ibase); - if (!icp) - continue; - - dt_add_property_strings(icp, "compatible", - "IBM,ppc-xicp", - "IBM,power7-xicp"); - - irange[0] = dt_property_get_cell(intsrv, 0); /* Index */ - irange[1] = num_threads; /* num servers */ - dt_add_property(icp, "ibm,interrupt-server-ranges", - irange, sizeof(irange)); - dt_add_property(icp, "interrupt-controller", NULL, 0); - dt_add_property_cells(icp, "#address-cells", 0); - dt_add_property_string(icp, "device_type", - "PowerPC-External-Interrupt-Presentation"); - for (i = 0; i < num_threads*2; i += 2) { - reg[i] = ibase; - /* One page is enough for a handful of regs. */ - reg[i+1] = 4096; - ibase += reg[i+1]; - } - dt_add_property(icp, "reg", reg, sizeof(reg)); - } -} - -static bool __paca_parse(void) -{ - const struct HDIF_common_hdr *paca; - struct dt_node *cpus; - - paca = get_hdif(&spira.ntuples.paca, PACA_HDIF_SIG); - if (!paca) { - prerror("Invalid PACA (PCIA = %p)\n", - ntuple_addr(&spira.ntuples.pcia)); - return false; - } - - if (be32_to_cpu(spira.ntuples.paca.act_len) < sizeof(*paca)) { - prerror("PACA: invalid size %u\n", - be32_to_cpu(spira.ntuples.paca.act_len)); - return false; - } - - cpus = dt_new(dt_root, "cpus"); - dt_add_property_cells(cpus, "#address-cells", 1); - dt_add_property_cells(cpus, "#size-cells", 0); - - for_each_paca(paca) { - const struct sppaca_cpu_id *id; - u32 size, ve_flags; - bool okay; - - id = HDIF_get_idata(paca, SPPACA_IDATA_CPU_ID, &size); - - /* The ID structure on Blade314 is only 0x54 long. We can - * cope with it as we don't use all the additional fields. - * The minimum size we support is 0x40 - */ - if (!id || size < SPIRA_CPU_ID_MIN_SIZE) { - prerror("CPU[%i]: bad id size %u @ %p\n", - paca_index(paca), size, id); - return false; - } - - ve_flags = be32_to_cpu(id->verify_exists_flags); - switch ((ve_flags&CPU_ID_VERIFY_MASK) >> CPU_ID_VERIFY_SHIFT) { - case CPU_ID_VERIFY_USABLE_NO_FAILURES: - case CPU_ID_VERIFY_USABLE_FAILURES: - okay = true; - break; - default: - okay = false; - } - - prlog(PR_INFO, "CPU[%i]: PIR=%i RES=%i %s\n", - paca_index(paca), be32_to_cpu(id->pir), - be32_to_cpu(id->process_interrupt_line), - okay ? "OK" : "UNAVAILABLE"); - - /* Secondary threads don't get their own node. */ - if (ve_flags & CPU_ID_SECONDARY_THREAD) - continue; - - if (!add_cpu_node(cpus, paca, id, okay)) - return false; - } - - /* Now account for secondaries. */ - for_each_paca(paca) { - const struct dt_property *prop; - const struct sppaca_cpu_id *id; - u32 size, state, num, ve_flags; - struct dt_node *cpu; - __be32 *new_prop; - - id = HDIF_get_idata(paca, 2, &size); - if (!CHECK_SPPTR(id)) - continue; - - ve_flags = be32_to_cpu(id->verify_exists_flags); - state = (ve_flags & CPU_ID_VERIFY_MASK) >> CPU_ID_VERIFY_SHIFT; - switch (state) { - case CPU_ID_VERIFY_USABLE_NO_FAILURES: - case CPU_ID_VERIFY_USABLE_FAILURES: - break; - default: - continue; - } - - /* Only interested in secondary threads. */ - if (!(ve_flags & CPU_ID_SECONDARY_THREAD)) - continue; - - cpu = find_cpu_by_hardware_proc_id(cpus, - be32_to_cpu(id->hardware_proc_id)); - if (!cpu) { - prerror("CPU[%i]: could not find primary hwid %i\n", - paca_index(paca), - be32_to_cpu(id->hardware_proc_id)); - return false; - } - - /* Add the cpu #. */ - prop = dt_find_property(cpu, "ibm,ppc-interrupt-server#s"); - if (!prop) { - prerror("CPU[%i]: could not find mapping information\n", - paca_index(paca)); - return false; - } - num = prop->len / sizeof(u32); - new_prop = malloc((num + 1) * sizeof(u32)); - if (!new_prop) { - prerror("Property allocation length %zu failed\n", - (num + 1) * sizeof(u32)); - return false; - } - memcpy(new_prop, prop->prop, prop->len); - add_be32_sorted(new_prop, id->process_interrupt_line, num); - dt_del_property(cpu, (struct dt_property *)prop); - dt_add_property(cpu, "ibm,ppc-interrupt-server#s", - new_prop, (num + 1) * sizeof(__be32)); - free(new_prop); - } - - /* - * P7 and P8 use the XICS interrupt controller which has a per-core - * interrupt controller node. - */ - if (proc_gen <= proc_gen_p8) - add_xics_icps(); - - return true; -} - -int paca_parse(void) -{ - if (!__paca_parse()) { - prerror("CPU: Initial CPU parsing failed\n"); - return -1; - } - return 0; -} diff --git a/hdata/pcia.c b/hdata/pcia.c index ff645ab..8e3b961 100644 --- a/hdata/pcia.c +++ b/hdata/pcia.c @@ -114,7 +114,7 @@ static struct dt_node *add_core_node(struct dt_node *cpus, prlog(PR_INFO, "CORE[%i]: PIR=%.8x %s %s(%u threads)\n", pcia_index(pcia), be32_to_cpu(t->pir), - ve_flags & CPU_ID_PACA_RESERVED + ve_flags & CPU_ID_PCIA_RESERVED ? "**RESERVED**" : cpu_state(ve_flags), be32_to_cpu(t->pir) == boot_cpu->pir ? "[boot] " : "", threads); @@ -168,7 +168,7 @@ static struct dt_node *add_core_node(struct dt_node *cpus, dt_add_property(cpu, "ibm,ppc-interrupt-server#s", iserv, 4 * threads); /* Add the ICP node for this CPU for P8 */ - if (proc_gen <= proc_gen_p8) + if (proc_gen == proc_gen_p8) add_xics_icp(pcia, threads, icp_compat); return cpu; @@ -179,7 +179,6 @@ bool pcia_parse(void) const void *pcia; struct dt_node *cpus; - /* Check PCIA exists... if not, maybe we are getting a PACA ? */ pcia = get_hdif(&spira.ntuples.pcia, "SPPCIA"); if (!pcia) return false; diff --git a/hdata/spira.c b/hdata/spira.c index 8b4e3cb..6e4da3c 100644 --- a/hdata/spira.c +++ b/hdata/spira.c @@ -847,7 +847,7 @@ static void add_nx_node(u32 gcid) "ibm,power8-nx"); break; case proc_gen_p9: - /* POWER9 NX is not software compatible with P7/P8 NX */ + /* POWER9 NX is not software compatible with P8 NX */ dt_add_property_strings(nx, "compatible", "ibm,power9-nx"); break; default: @@ -1295,10 +1295,6 @@ static void add_iplparams(void) * numbering used by HDAT to reference chips, which doesn't correspond * to the HW IDs. We want to use the HW IDs everywhere in the DT so * we convert using this. - * - * Note: On P7, the HW ID is the XSCOM "GCID" including the T bit which - * is *different* from the chip ID portion of the interrupt server# - * (or PIR). See the explanations in chip.h */ uint32_t pcid_to_chip_id(uint32_t proc_chip_id) { @@ -1734,10 +1730,9 @@ int parse_hdat(bool is_opal) /* Create /ibm,opal/led node */ dt_init_led_node(); - /* Parse SPPACA and/or PCIA */ + /* Parse PCIA */ if (!pcia_parse()) - if (paca_parse() < 0) - return -1; + return -1; /* IPL params */ add_iplparams(); diff --git a/hdata/spira.h b/hdata/spira.h index eb5d1ea..2c944be 100644 --- a/hdata/spira.h +++ b/hdata/spira.h @@ -73,7 +73,7 @@ struct spira { struct spira_ntuples ntuples; /* * We reserve 0xc0 rather than 0x4c0 so we fit SPIRAH/SPIRAS here - * while preserving compatibility with existing P7/P8 systems. + * while preserving compatibility with existing P8 systems. * * According to FSP engineers, this is an okay thing to do. */ @@ -180,11 +180,8 @@ extern struct HDIF_common_hdr *__get_hdif(struct spira_ntuple *n, be32_to_cpu((_ntuples)->alloc_len)); \ _p = (void *)_p + be32_to_cpu((_ntuples)->alloc_len)) -#define for_each_paca(p) for_each_ntuple(&spira.ntuples.paca, p, PACA_HDIF_SIG) - #define for_each_pcia(p) for_each_ntuple(&spira.ntuples.pcia, p, SPPCIA_HDIF_SIG) - /* We override these for testing. */ #ifndef ntuple_addr #define ntuple_addr(_ntuples) ((void *)BE64_TO_CPU((_ntuples)->addr)) @@ -930,24 +927,18 @@ struct slca_entry { /* - * SPPACA structure. The SPIRA contain an array of these, one - * per processor thread + * SPPCIA structure. The SPIRA contain an array of these, one + * per processor core */ -#define PACA_HDIF_SIG "SPPACA" - -/* Idata index 0 : FRU ID Data */ -#define SPPACA_IDATA_FRU_ID 0 - -/* Idata index 1 : Keyword VPD */ -#define SPPACA_IDATA_KW_VPD 1 +#define SPPCIA_HDIF_SIG "SPPCIA" -/* Idata index 2 : CPU ID data area */ -#define SPPACA_IDATA_CPU_ID 2 +/* Idata index 0 : Core unique data */ +#define SPPCIA_IDATA_CORE_UNIQUE 0 -struct sppaca_cpu_id { - __be32 pir; - __be32 fru_id; - __be32 hardware_proc_id; +struct sppcia_core_unique { + __be32 reserved; + __be32 proc_fru_id; + __be32 hw_proc_id; #define CPU_ID_VERIFY_MASK 0xC0000000 #define CPU_ID_VERIFY_SHIFT 30 #define CPU_ID_VERIFY_USABLE_NO_FAILURES 0 @@ -955,45 +946,43 @@ struct sppaca_cpu_id { #define CPU_ID_VERIFY_NOT_INSTALLED 2 #define CPU_ID_VERIFY_UNUSABLE 3 #define CPU_ID_SECONDARY_THREAD 0x20000000 -#define CPU_ID_PACA_RESERVED 0x10000000 +#define CPU_ID_PCIA_RESERVED 0x10000000 #define CPU_ID_NUM_SECONDARY_THREAD_MASK 0x00FF0000 #define CPU_ID_NUM_SECONDARY_THREAD_SHIFT 16 - __be32 verify_exists_flags; + __be32 verif_exist_flags; __be32 chip_ec_level; - __be32 processor_chip_id; - __be32 logical_processor_id; - /* This is the resource number, too. */ - __be32 process_interrupt_line; - __be32 reserved1; - __be32 hardware_module_id; - __be64 ibase; - __be32 deprecated1; - __be32 physical_thread_id; - __be32 deprecated2; + __be32 proc_chip_id; + __be32 reserved2; + __be32 reserved3; + __be32 reserved4; + __be32 hw_module_id; + __be64 reserved5; + __be32 reserved6; + __be32 reserved7; + __be32 reserved8; __be32 ccm_node_id; - /* This fields are not always present, check struct size */ -#define SPIRA_CPU_ID_MIN_SIZE 0x40 __be32 hw_card_id; __be32 internal_drawer_node_id; __be32 drawer_book_octant_blade_id; __be32 memory_interleaving_scope; __be32 lco_target; + __be32 reserved9; } __packed; -/* Idata index 3 : Timebase data */ -#define SPPACA_IDATA_TIMEBASE 3 +/* Idata index 1 : CPU Time base structure */ +#define SPPCIA_IDATA_TIMEBASE 1 -struct sppaca_cpu_timebase { +struct sppcia_cpu_timebase { __be32 cycle_time; __be32 time_base; __be32 actual_clock_speed; __be32 memory_bus_frequency; } __packed; -/* Idata index 4 : Cache size structure */ -#define SPPACA_IDATA_CACHE_SIZE 4 +/* Idata index 2 : CPU Cache Size Structure */ +#define SPPCIA_IDATA_CPU_CACHE 2 -struct sppaca_cpu_cache { +struct sppcia_cpu_cache { __be32 icache_size_kb; __be32 icache_line_size; __be32 l1_dcache_size_kb; @@ -1016,57 +1005,6 @@ struct sppaca_cpu_cache { __be32 l35_cache_line_size; } __packed; -/* Idata index 6 : CPU Attributes */ -#define SPPACA_IDATA_CPU_ATTR 6 - -#define sppaca_cpu_attr sppcia_cpu_attr - -/* - * SPPCIA structure. The SPIRA contain an array of these, one - * per processor core - */ -#define SPPCIA_HDIF_SIG "SPPCIA" - -/* Idata index 0 : Core unique data */ -#define SPPCIA_IDATA_CORE_UNIQUE 0 - -/* NOTE: This is the same layout as "struct sppaca_cpu_id", - * with essentially some fields removed and a reserved - * field added - */ -struct sppcia_core_unique { - __be32 reserved; - __be32 proc_fru_id; - __be32 hw_proc_id; - __be32 verif_exist_flags; /* Same as PACA */ - __be32 chip_ec_level; - __be32 proc_chip_id; - __be32 reserved2; - __be32 reserved3; - __be32 reserved4; - __be32 hw_module_id; - __be64 reserved5; - __be32 reserved6; - __be32 reserved7; - __be32 reserved8; - __be32 ccm_node_id; - __be32 hw_card_id; - __be32 internal_drawer_node_id; - __be32 drawer_book_octant_blade_id; - __be32 memory_interleaving_scope; - __be32 lco_target; - __be32 reserved9; -} __packed; - -/* Idata index 1 : CPU Time base structure */ -#define SPPCIA_IDATA_TIMEBASE 1 - -#define sppcia_cpu_timebase sppaca_cpu_timebase - -/* Idata index 2 : CPU Cache Size Structure */ -#define SPPCIA_IDATA_CPU_CACHE 2 - -#define sppcia_cpu_cache sppaca_cpu_cache /* Idata index 3 : Thread Array Data * diff --git a/hdata/test/hdata_to_dt.c b/hdata/test/hdata_to_dt.c index e1258f1..4605d50 100644 --- a/hdata/test/hdata_to_dt.c +++ b/hdata/test/hdata_to_dt.c @@ -136,7 +136,6 @@ static bool spira_check_ptr(const void *ptr, const char *file, unsigned int line #include "../hdif.c" #include "../iohub.c" #include "../memory.c" -#include "../paca.c" #include "../pcia.c" #include "../spira.c" #include "../vpd.c" @@ -339,7 +338,7 @@ int main(int argc, char *argv[]) " -8E Force PVR to POWER8E\n" " -9 Force PVR to POWER9 (nimbus)\n" "\n" - "When no PVR is specified -7 is assumed" + "When no PVR is specified -8 is assumed" "\n" "Pipe to 'dtc -I dtb -O dts' for human readable output\n"); } diff --git a/hdata/vpd.c b/hdata/vpd.c index a29155a..3c480b4 100644 --- a/hdata/vpd.c +++ b/hdata/vpd.c @@ -702,7 +702,6 @@ static void iohub_vpd_parse(void) continue; } - /* On P7, the keyword VPD will not be NULL */ if (HDIF_get_idata(iohub_hdr, CECHUB_ASCII_KEYWORD_VPD, &vpd_sz)) dt_add_vpd_node(iohub_hdr, CECHUB_FRU_ID_DATA, diff --git a/hw/fsp/fsp-console.c b/hw/fsp/fsp-console.c index 42fb988..1a2ecab 100644 --- a/hw/fsp/fsp-console.c +++ b/hw/fsp/fsp-console.c @@ -1015,53 +1015,31 @@ void fsp_console_add_nodes(void) void fsp_console_select_stdout(void) { bool use_serial = false; + int rc; + u8 param; if (!fsp_present()) return; - /* On P8, we have a sysparam ! yay ! */ - if (proc_gen >= proc_gen_p8) { - int rc; - u8 param; - - rc = fsp_get_sys_param(SYS_PARAM_CONSOLE_SELECT, - ¶m, 1, NULL, NULL); - if (rc != 1) - prerror("FSPCON: Failed to get console" - " sysparam rc %d\n", rc); - else { - switch(param) { - case 0: - use_serial = false; - break; - case 1: - use_serial = true; - break; - default: - prerror("FSPCON: Unknown console" - " sysparam %d\n", param); - } - } + rc = fsp_get_sys_param(SYS_PARAM_CONSOLE_SELECT, + ¶m, 1, NULL, NULL); + if (rc != 1) { + prerror("FSPCON: Failed to get console" + " sysparam rc %d\n", rc); } else { - struct dt_node *iplp; - u32 ipl_mode = 0; - - /* - * We hijack the "os-ipl-mode" setting in iplparams to select - * out output console. This is the "i5/OS partition mode boot" - * setting in ASMI converted to an integer: 0=A, 1=B. - */ - iplp = dt_find_by_path(dt_root, "ipl-params/ipl-params"); - if (iplp) { - ipl_mode = dt_prop_get_u32_def(iplp, "os-ipl-mode", 0); - use_serial = ipl_mode > 0; - - /* - * Now, if ipl_mode is > 0, we use serial port A else - * we use IPMI/SOL/DVS - */ + switch(param) { + case 0: + use_serial = false; + break; + case 1: + use_serial = true; + break; + default: + prerror("FSPCON: Unknown console" + " sysparam %d\n", param); } } + dt_check_del_prop(dt_chosen, "linux,stdout-path"); if (fsp_serials[1].open && use_serial) { diff --git a/hw/fsp/fsp-occ.c b/hw/fsp/fsp-occ.c index d48c28f..8164129 100644 --- a/hw/fsp/fsp-occ.c +++ b/hw/fsp/fsp-occ.c @@ -410,10 +410,6 @@ static struct fsp_client fsp_occ_client = { void occ_fsp_init(void) { - /* OCC is supported in P8 and P9 */ - if (proc_gen < proc_gen_p8) - return; - /* If we have an FSP, register for notifications */ if (fsp_present()) fsp_register_client(&fsp_occ_client, FSP_MCLASS_OCC); diff --git a/hw/fsp/fsp-sysdump.c b/hw/fsp/fsp-sysdump.c index cf4af34..fd915f4 100644 --- a/hw/fsp/fsp-sysdump.c +++ b/hw/fsp/fsp-sysdump.c @@ -64,12 +64,6 @@ static int max_dump_size = MIN(MAX_SAPPHIRE_DUMP_SIZE, PSI_DMA_HYP_DUMP_SIZE); /* Protect MDST table entries */ static struct lock mdst_lock = LOCK_UNLOCKED; -/* Not supported on P7 */ -static inline bool fsp_mdst_supported(void) -{ - return proc_gen >= proc_gen_p8; -} - static inline uint32_t get_dump_region_map_size(uint64_t addr, uint32_t size) { uint64_t start, end; @@ -280,11 +274,6 @@ static int64_t fsp_opal_register_dump_region(uint32_t id, if (!fsp_present()) return OPAL_UNSUPPORTED; - if (!fsp_mdst_supported()) { - printf("MDST: Not supported\n"); - return OPAL_UNSUPPORTED; - } - /* Validate memory region id */ if (id < DUMP_REGION_HOST_START || id > DUMP_REGION_HOST_END) { log_simple_error(&e_info(OPAL_RC_DUMP_MDST_ADD), @@ -315,11 +304,6 @@ static int64_t fsp_opal_unregister_dump_region(uint32_t id) if (!fsp_present()) return OPAL_UNSUPPORTED; - if (!fsp_mdst_supported()) { - printf("MDST: Not supported\n"); - return OPAL_UNSUPPORTED; - } - /* Validate memory region id */ if (id < DUMP_REGION_HOST_START || id > DUMP_REGION_HOST_END) { log_simple_error(&e_info(OPAL_RC_DUMP_MDST_REMOVE), @@ -407,9 +391,6 @@ void fsp_mdst_table_init(void) opal_register(OPAL_UNREGISTER_DUMP_REGION, fsp_opal_unregister_dump_region, 1); - if (!fsp_mdst_supported()) - return; - /* Initiate MDST */ if (mdst_table_init() != OPAL_SUCCESS) return; diff --git a/hw/fsp/fsp.c b/hw/fsp/fsp.c index 6fa6534..f368998 100644 --- a/hw/fsp/fsp.c +++ b/hw/fsp/fsp.c @@ -1844,10 +1844,7 @@ static void fsp_init_tce_table(void) { fsp_tce_table = (u64 *)PSI_TCE_TABLE_BASE; - /* Memset the larger table even if we only use the smaller - * one on P7 - */ - memset(fsp_tce_table, 0, PSI_TCE_TABLE_SIZE_P8); + memset(fsp_tce_table, 0, PSI_TCE_TABLE_SIZE); } void fsp_tce_map(u32 offset, void *addr, u32 size) @@ -988,7 +988,6 @@ static const struct phb_ops npu_ops = { .cfg_write8 = npu_cfg_write8, .cfg_write16 = npu_cfg_write16, .cfg_write32 = npu_cfg_write32, - .choose_bus = NULL, .get_reserved_pe_number = NULL, .device_init = NULL, .phb_final_fixup = npu_phb_final_fixup, diff --git a/hw/npu2-opencapi.c b/hw/npu2-opencapi.c index e2319f2..ed6650f 100644 --- a/hw/npu2-opencapi.c +++ b/hw/npu2-opencapi.c @@ -1862,7 +1862,6 @@ static const struct phb_ops npu2_opencapi_ops = { .cfg_write8 = npu2_opencapi_pcicfg_write8, .cfg_write16 = npu2_opencapi_pcicfg_write16, .cfg_write32 = npu2_opencapi_pcicfg_write32, - .choose_bus = NULL, .device_init = NULL, .phb_final_fixup = npu2_opencapi_final_fixup, .ioda_reset = npu2_opencapi_ioda_reset, @@ -1292,7 +1292,6 @@ static const struct phb_ops npu_ops = { .cfg_write8 = npu2_cfg_write8, .cfg_write16 = npu2_cfg_write16, .cfg_write32 = npu2_cfg_write32, - .choose_bus = NULL, .device_init = NULL, .phb_final_fixup = npu2_phb_final_fixup, .ioda_reset = npu2_ioda_reset, diff --git a/hw/nx-842.c b/hw/nx-842.c index fd6f74c..933f2df 100644 --- a/hw/nx-842.c +++ b/hw/nx-842.c @@ -118,13 +118,10 @@ static int nx_cfg_842_dma(u32 gcid, u64 xcfg) return rc; } - if (proc_gen >= proc_gen_p8) { - cfg = SETFIELD(NX_DMA_CFG_842_COMPRESS_PREFETCH, cfg, - DMA_COMPRESS_PREFETCH); - cfg = SETFIELD(NX_DMA_CFG_842_DECOMPRESS_PREFETCH, cfg, - DMA_DECOMPRESS_PREFETCH); - } - + cfg = SETFIELD(NX_DMA_CFG_842_COMPRESS_PREFETCH, cfg, + DMA_COMPRESS_PREFETCH); + cfg = SETFIELD(NX_DMA_CFG_842_DECOMPRESS_PREFETCH, cfg, + DMA_DECOMPRESS_PREFETCH); cfg = SETFIELD(NX_DMA_CFG_842_COMPRESS_MAX_RR, cfg, DMA_COMPRESS_MAX_RR); cfg = SETFIELD(NX_DMA_CFG_842_DECOMPRESS_MAX_RR, cfg, @@ -1719,10 +1719,6 @@ void occ_pstates_init(void) u8 domain_runs_at; static bool occ_pstates_initialized; - /* OCC is supported in P8 and P9 */ - if (proc_gen < proc_gen_p8) - return; - power_mgt = dt_find_by_path(dt_root, "/ibm,opal/power-mgt"); if (!power_mgt) { /** @@ -1969,8 +1965,8 @@ void occ_send_dummy_interrupt(void) struct psi *psi; struct proc_chip *chip = get_chip(this_cpu()->chip_id); - /* Emulators and P7 doesn't do this */ - if (proc_gen < proc_gen_p8 || chip_quirk(QUIRK_NO_OCC_IRQ)) + /* Emulators don't do this */ + if (chip_quirk(QUIRK_NO_OCC_IRQ)) return; /* Find a functional PSI. This ensures an interrupt even if @@ -336,16 +336,6 @@ PHB3_PCI_CFG_WRITE(8, u8) PHB3_PCI_CFG_WRITE(16, u16) PHB3_PCI_CFG_WRITE(32, u32) -static uint8_t phb3_choose_bus(struct phb *phb __unused, - struct pci_device *bridge __unused, - uint8_t candidate, uint8_t *max_bus __unused, - bool *use_max) -{ - /* Use standard bus number selection */ - *use_max = false; - return candidate; -} - static int64_t phb3_get_reserved_pe_number(struct phb *phb __unused) { return PHB3_RESERVED_PE_NUM; @@ -3857,7 +3847,6 @@ static const struct phb_ops phb3_ops = { .cfg_write8 = phb3_pcicfg_write8, .cfg_write16 = phb3_pcicfg_write16, .cfg_write32 = phb3_pcicfg_write32, - .choose_bus = phb3_choose_bus, .get_reserved_pe_number = phb3_get_reserved_pe_number, .device_init = phb3_device_init, .device_remove = phb3_device_remove, @@ -601,16 +601,6 @@ PHB4_PCI_CFG_WRITE(8, u8) PHB4_PCI_CFG_WRITE(16, u16) PHB4_PCI_CFG_WRITE(32, u32) -static uint8_t phb4_choose_bus(struct phb *phb __unused, - struct pci_device *bridge __unused, - uint8_t candidate, uint8_t *max_bus __unused, - bool *use_max) -{ - /* Use standard bus number selection */ - *use_max = false; - return candidate; -} - static int64_t phb4_get_reserved_pe_number(struct phb *phb) { struct phb4 *p = phb_to_phb4(phb); @@ -4795,7 +4785,6 @@ static const struct phb_ops phb4_ops = { .cfg_write8 = phb4_pcicfg_write8, .cfg_write16 = phb4_pcicfg_write16, .cfg_write32 = phb4_pcicfg_write32, - .choose_bus = phb4_choose_bus, .get_reserved_pe_number = phb4_get_reserved_pe_number, .device_init = phb4_device_init, .device_remove = NULL, @@ -818,7 +818,8 @@ static void psi_create_mm_dtnode(struct psi *psi) psi_create_p9_int_map(psi, np); break; default: - dt_add_property_strings(np, "compatible", "ibm,psi"); + assert(0); + break; } dt_add_property_cells(np, "interrupt-parent", get_ics_phandle()); dt_add_property_cells(np, "interrupts", psi->interrupt, 1); @@ -1061,9 +1061,6 @@ int64_t slw_reinit(uint64_t flags) bool has_waker = false; bool target_le = slw_current_le; - if (proc_gen < proc_gen_p8) - return OPAL_UNSUPPORTED; - if (flags & OPAL_REINIT_CPUS_HILE_BE) target_le = false; if (flags & OPAL_REINIT_CPUS_HILE_LE) @@ -61,7 +61,7 @@ static inline void *xscom_addr(uint32_t gcid, uint32_t pcb_addr) assert(chip); addr = chip->xscom_base; - if (proc_gen <= proc_gen_p8) { + if (proc_gen == proc_gen_p8) { addr |= ((uint64_t)pcb_addr << 4) & ~0xfful; addr |= (pcb_addr << 3) & 0x78; } else @@ -432,11 +432,6 @@ static int xscom_indirect_read_form0(uint32_t gcid, uint64_t pcb_addr, uint64_t data; int rc, retries; - if (proc_gen < proc_gen_p8) { - *val = (uint64_t)-1; - return OPAL_UNSUPPORTED; - } - /* Write indirect address */ addr = pcb_addr & 0x7fffffff; data = XSCOM_DATA_IND_READ | @@ -491,9 +486,6 @@ static int xscom_indirect_write_form0(uint32_t gcid, uint64_t pcb_addr, uint64_t data; int rc, retries; - if (proc_gen < proc_gen_p8) - return OPAL_UNSUPPORTED; - /* Only 16 bit data with indirect */ if (val & ~(XSCOM_ADDR_IND_DATA)) return OPAL_PARAMETER; diff --git a/include/chip.h b/include/chip.h index adb962a..f14e78b 100644 --- a/include/chip.h +++ b/include/chip.h @@ -34,9 +34,7 @@ * | | | * |___|___|___|___|___|___| * - * The difference with P7 is the absence of T bit, the ChipID - * is 3 bits long. The GCID is thus the same as the high bits - * if the PIR + * The the ChipID is 3 bits long, the GCID is the same as the high bits of PIR */ #define P8_PIR2GCID(pir) (((pir) >> 7) & 0x3f) diff --git a/include/mem-map.h b/include/mem-map.h index 9914651..61ecac3 100644 --- a/include/mem-map.h +++ b/include/mem-map.h @@ -99,7 +99,7 @@ /* This is our PSI TCE table. It's 256K entries on P8 */ #define PSI_TCE_TABLE_BASE (SKIBOOT_BASE + 0x01a00000) -#define PSI_TCE_TABLE_SIZE_P8 0x00200000UL +#define PSI_TCE_TABLE_SIZE 0x00200000UL /* This is our dump result table after MPIPL. Hostboot will write to this * memory after moving memory content from source to destination memory. diff --git a/include/nx.h b/include/nx.h index 675d17a..4950a2d 100644 --- a/include/nx.h +++ b/include/nx.h @@ -86,7 +86,7 @@ #define NX_EE_CFG_CH7 PPC_BIT(53) /* AMF */ #define NX_EE_CFG_CH6 PPC_BIT(54) /* AMF */ #define NX_EE_CFG_CH5 PPC_BIT(55) /* AMF */ -#define NX_EE_CFG_CH4 PPC_BIT(56) /* P7: SYM, P8: AMF */ +#define NX_EE_CFG_CH4 PPC_BIT(56) /* AMF */ #define NX_EE_CFG_CH3 PPC_BIT(57) /* SYM */ #define NX_EE_CFG_CH2 PPC_BIT(58) /* SYM */ #define NX_P9_EE_CFG_CH4 PPC_BIT(61) /* gzip */ diff --git a/include/pci.h b/include/pci.h index 8169fe6..fb91d79 100644 --- a/include/pci.h +++ b/include/pci.h @@ -218,12 +218,6 @@ struct phb_ops { int64_t (*cfg_write32)(struct phb *phb, uint32_t bdfn, uint32_t offset, uint32_t data); - /* - * Bus number selection. See pci_scan() for a description - */ - uint8_t (*choose_bus)(struct phb *phb, struct pci_device *bridge, - uint8_t candidate, uint8_t *max_bus, - bool *use_max); int64_t (*get_reserved_pe_number)(struct phb *phb); /* |