diff options
| -rw-r--r-- | hw/chiptod.c | 3 | ||||
| -rw-r--r-- | hw/lpc.c | 27 | ||||
| -rw-r--r-- | hw/p8-i2c.c | 45 | ||||
| -rw-r--r-- | hw/xscom.c | 10 | ||||
| -rw-r--r-- | include/gx.h | 18 | ||||
| -rw-r--r-- | include/p5ioc2-regs.h | 50 | ||||
| -rw-r--r-- | include/p7ioc-regs.h | 134 | ||||
| -rw-r--r-- | include/pci-cfg.h | 116 | ||||
| -rw-r--r-- | include/phb3-regs.h | 156 | ||||
| -rw-r--r-- | include/processor.h | 30 | ||||
| -rw-r--r-- | include/psi.h | 6 |
11 files changed, 200 insertions, 395 deletions
diff --git a/hw/chiptod.c b/hw/chiptod.c index 88bc466..49b84e7 100644 --- a/hw/chiptod.c +++ b/hw/chiptod.c @@ -42,8 +42,7 @@ /* -- TOD PIB Master reg -- */ #define TOD_PIB_MASTER 0x00040027 #define TOD_PIBM_ADDR_CFG_MCAST PPC_BIT(25) -#define TOD_PIBM_ADDR_CFG_SLADDR_MASK PPC_BITMASK(26,31) -#define TOD_PIBM_ADDR_CFG_SLADDR_LSH PPC_BITLSHIFT(31) +#define TOD_PIBM_ADDR_CFG_SLADDR PPC_BITMASK(26,31) /* -- TOD Error interrupt register -- */ #define TOD_ERROR 0x00040030 @@ -37,29 +37,22 @@ DEFINE_LOG_ENTRY(OPAL_RC_LPC_WRITE, OPAL_PLATFORM_ERR_EVT, OPAL_LPC, #define ECCB_DATA 3 /* b0023 -> b00218 */ #define ECCB_CTL_MAGIC 0xd000000000000000ul -#define ECCB_CTL_DATASZ_MASK PPC_BITMASK(4,7) -#define ECCB_CTL_DATASZ_LSH PPC_BITLSHIFT(7) +#define ECCB_CTL_DATASZ PPC_BITMASK(4,7) #define ECCB_CTL_READ PPC_BIT(15) -#define ECCB_CTL_ADDRLEN_MASK PPC_BITMASK(23,25) -#define ECCB_CTL_ADDRLEN_LSH PPC_BITLSHIFT(25) +#define ECCB_CTL_ADDRLEN PPC_BITMASK(23,25) #define ECCB_ADDRLEN_4B 0x4 -#define ECCB_CTL_ADDR_MASK PPC_BITMASK(32,63) -#define ECCB_CTL_ADDR_LSH 0 +#define ECCB_CTL_ADDR PPC_BITMASK(32,63) -#define ECCB_STAT_PIB_ERR_MASK PPC_BITMASK(0,5) -#define ECCB_STAT_PIB_ERR_LSH PPC_BITLSHIFT(5) -#define ECCB_STAT_RD_DATA_MASK PPC_BITMASK(6,37) -#define ECCB_STAT_RD_DATA_LSH PPC_BITLSHIFT(37) +#define ECCB_STAT_PIB_ERR PPC_BITMASK(0,5) +#define ECCB_STAT_RD_DATA PPC_BITMASK(6,37) #define ECCB_STAT_BUSY PPC_BIT(44) -#define ECCB_STAT_ERRORS1_MASK PPC_BITMASK(45,51) -#define ECCB_STAT_ERRORS1_LSH PPC_BITLSHIFT(51) +#define ECCB_STAT_ERRORS1 PPC_BITMASK(45,51) #define ECCB_STAT_OP_DONE PPC_BIT(52) -#define ECCB_STAT_ERRORS2_MASK PPC_BITMASK(53,55) -#define ECCB_STAT_ERRORS3_LSH PPC_BITLSHIFT(55) +#define ECCB_STAT_ERRORS2 PPC_BITMASK(53,55) -#define ECCB_STAT_ERR_MASK (ECCB_STAT_PIB_ERR_MASK | \ - ECCB_STAT_ERRORS1_MASK | \ - ECCB_STAT_ERRORS2_MASK) +#define ECCB_STAT_ERR_MASK (ECCB_STAT_PIB_ERR | \ + ECCB_STAT_ERRORS1 | \ + ECCB_STAT_ERRORS2) #define ECCB_TIMEOUT 1000000 diff --git a/hw/p8-i2c.c b/hw/p8-i2c.c index f7074ad..47efafd 100644 --- a/hw/p8-i2c.c +++ b/hw/p8-i2c.c @@ -66,8 +66,7 @@ DEFINE_LOG_ENTRY(OPAL_RC_I2C_RESET, OPAL_INPUT_OUTPUT_ERR_EVT, OPAL_I2C, /* I2C FIFO register */ #define I2C_FIFO_REG 0x4 -#define I2C_FIFO_MASK PPC_BITMASK(0, 7) -#define I2C_FIFO_LSH PPC_BITLSHIFT(7) +#define I2C_FIFO PPC_BITMASK(0, 7) /* I2C command register */ #define I2C_CMD_REG 0x5 @@ -75,19 +74,15 @@ DEFINE_LOG_ENTRY(OPAL_RC_I2C_RESET, OPAL_INPUT_OUTPUT_ERR_EVT, OPAL_I2C, #define I2C_CMD_WITH_ADDR PPC_BIT(1) #define I2C_CMD_READ_CONT PPC_BIT(2) #define I2C_CMD_WITH_STOP PPC_BIT(3) -#define I2C_CMD_DEV_ADDR_MASK PPC_BITMASK(8, 14) -#define I2C_CMD_DEV_ADDR_LSH PPC_BITLSHIFT(14) +#define I2C_CMD_DEV_ADDR PPC_BITMASK(8, 14) #define I2C_CMD_READ_NOT_WRITE PPC_BIT(15) -#define I2C_CMD_LEN_BYTES_MASK PPC_BITMASK(16, 31) -#define I2C_CMD_LEN_BYTES_LSH PPC_BITLSHIFT(31) +#define I2C_CMD_LEN_BYTES PPC_BITMASK(16, 31) #define I2C_MAX_TFR_LEN 0xfff0ull /* I2C mode register */ #define I2C_MODE_REG 0x6 -#define I2C_MODE_BIT_RATE_DIV_MASK PPC_BITMASK(0, 15) -#define I2C_MODE_BIT_RATE_DIV_LSH PPC_BITLSHIFT(15) -#define I2C_MODE_PORT_NUM_MASK PPC_BITMASK(16, 21) -#define I2C_MODE_PORT_NUM_LSH PPC_BITLSHIFT(21) +#define I2C_MODE_BIT_RATE_DIV PPC_BITMASK(0, 15) +#define I2C_MODE_PORT_NUM PPC_BITMASK(16, 21) #define I2C_MODE_ENHANCED PPC_BIT(28) #define I2C_MODE_DIAGNOSTIC PPC_BIT(29) #define I2C_MODE_PACING_ALLOW PPC_BIT(30) @@ -95,17 +90,14 @@ DEFINE_LOG_ENTRY(OPAL_RC_I2C_RESET, OPAL_INPUT_OUTPUT_ERR_EVT, OPAL_I2C, /* I2C watermark register */ #define I2C_WATERMARK_REG 0x7 -#define I2C_WATERMARK_HIGH_MASK PPC_BITMASK(16, 19) -#define I2C_WATERMARK_HIGH_LSH PPC_BITLSHIFT(19) -#define I2C_WATERMARK_LOW_MASK PPC_BITMASK(24, 27) -#define I2C_WATERMARK_LOW_LSH PPC_BITLSHIFT(27) +#define I2C_WATERMARK_HIGH PPC_BITMASK(16, 19) +#define I2C_WATERMARK_LOW PPC_BITMASK(24, 27) /* I2C interrupt mask, condition and interrupt registers */ #define I2C_INTR_MASK_REG 0x8 #define I2C_INTR_COND_REG 0x9 #define I2C_INTR_REG 0xa -#define I2C_INTR_ALL_MASK PPC_BITMASK(16, 31) -#define I2C_INTR_ALL_LSH PPC_BITLSHIFT(31) +#define I2C_INTR_ALL PPC_BITMASK(16, 31) #define I2C_INTR_INVALID_CMD PPC_BIT(16) #define I2C_INTR_LBUS_PARITY_ERR PPC_BIT(17) #define I2C_INTR_BKEND_OVERRUN_ERR PPC_BIT(18) @@ -135,16 +127,14 @@ DEFINE_LOG_ENTRY(OPAL_RC_I2C_RESET, OPAL_INPUT_OUTPUT_ERR_EVT, OPAL_I2C, #define I2C_STAT_DATA_REQ PPC_BIT(6) #define I2C_STAT_CMD_COMP PPC_BIT(7) #define I2C_STAT_STOP_ERR PPC_BIT(8) -#define I2C_STAT_UPPER_THRS_MASK PPC_BITMASK(9, 15) -#define I2C_STAT_UPPER_THRS_LSH PPC_BITLSHIFT(15) +#define I2C_STAT_UPPER_THRS PPC_BITMASK(9, 15) #define I2C_STAT_ANY_I2C_INTR PPC_BIT(16) #define I2C_STAT_PORT_HISTORY_BUSY PPC_BIT(19) #define I2C_STAT_SCL_INPUT_LEVEL PPC_BIT(20) #define I2C_STAT_SDA_INPUT_LEVEL PPC_BIT(21) #define I2C_STAT_PORT_BUSY PPC_BIT(22) #define I2C_STAT_INTERFACE_BUSY PPC_BIT(23) -#define I2C_STAT_FIFO_ENTRY_COUNT_MASK PPC_BITMASK(24, 31) -#define I2C_STAT_FIFO_ENTRY_COUNT_LSH PPC_BITLSHIFT(31) +#define I2C_STAT_FIFO_ENTRY_COUNT PPC_BITMASK(24, 31) #define I2C_STAT_ANY_ERR (I2C_STAT_INVALID_CMD | I2C_STAT_LBUS_PARITY_ERR | \ I2C_STAT_BKEND_OVERRUN_ERR | \ @@ -153,10 +143,8 @@ DEFINE_LOG_ENTRY(OPAL_RC_I2C_RESET, OPAL_INPUT_OUTPUT_ERR_EVT, OPAL_I2C, /* I2C extended status register */ #define I2C_EXTD_STAT_REG 0xc -#define I2C_EXTD_STAT_FIFO_SIZE_MASK PPC_BITMASK(0, 7) -#define I2C_EXTD_STAT_FIFO_SIZE_LSH PPC_BITLSHIFT(7) -#define I2C_EXTD_STAT_MSM_CURSTATE_MASK PPC_BITMASK(11, 15) -#define I2C_EXTD_STAT_MSM_CURSTATE_LSH PPC_BITLSHIFT(15) +#define I2C_EXTD_STAT_FIFO_SIZE PPC_BITMASK(0, 7) +#define I2C_EXTD_STAT_MSM_CURSTATE PPC_BITMASK(11, 15) #define I2C_EXTD_STAT_SCL_IN_SYNC PPC_BIT(16) #define I2C_EXTD_STAT_SDA_IN_SYNC PPC_BIT(17) #define I2C_EXTD_STAT_S_SCL PPC_BIT(18) @@ -167,15 +155,12 @@ DEFINE_LOG_ENTRY(OPAL_RC_I2C_RESET, OPAL_INPUT_OUTPUT_ERR_EVT, OPAL_I2C, #define I2C_EXTD_STAT_LOW_WATER PPC_BIT(23) #define I2C_EXTD_STAT_I2C_BUSY PPC_BIT(24) #define I2C_EXTD_STAT_SELF_BUSY PPC_BIT(25) -#define I2C_EXTD_STAT_I2C_VERSION_MASK PPC_BITMASK(27, 31) -#define I2C_EXTD_STAT_I2C_VERSION_LSH PPC_BITLSHIFT(31) +#define I2C_EXTD_STAT_I2C_VERSION PPC_BITMASK(27, 31) /* I2C residual front end/back end length */ #define I2C_RESIDUAL_LEN_REG 0xd -#define I2C_RESIDUAL_FRONT_END_MASK PPC_BITMASK(0, 15) -#define I2C_RESIDUAL_FRONT_END_LSH PPC_BITLSHIFT(15) -#define I2C_RESIDUAL_BACK_END_MASK PPC_BITMASK(16, 31) -#define I2C_RESIDUAL_BACK_END_LSH PPC_BITLSHIFT(31) +#define I2C_RESIDUAL_FRONT_END PPC_BITMASK(0, 15) +#define I2C_RESIDUAL_BACK_END PPC_BITMASK(16, 31) /* Port busy register */ #define I2C_PORT_BUYS_REG 0xe @@ -30,15 +30,13 @@ SPR_HMER_XSCOM_STATUS_MASK)) #define XSCOM_ADDR_IND_FLAG PPC_BIT(0) -#define XSCOM_ADDR_IND_ADDR_MASK PPC_BITMASK(12,31) -#define XSCOM_ADDR_IND_ADDR_LSH PPC_BITLSHIFT(31) -#define XSCOM_ADDR_IND_DATA_MSK PPC_BITMASK(48,63) +#define XSCOM_ADDR_IND_ADDR PPC_BITMASK(12,31) +#define XSCOM_ADDR_IND_DATA PPC_BITMASK(48,63) #define XSCOM_DATA_IND_READ PPC_BIT(0) #define XSCOM_DATA_IND_COMPLETE PPC_BIT(32) -#define XSCOM_DATA_IND_ERR_MASK PPC_BITMASK(33,35) -#define XSCOM_DATA_IND_ERR_LSH PPC_BITLSHIFT(35) -#define XSCOM_DATA_IND_DATA_MSK PPC_BITMASK(48,63) +#define XSCOM_DATA_IND_ERR PPC_BITMASK(33,35) +#define XSCOM_DATA_IND_DATA PPC_BITMASK(48,63) /* HB folks say: try 10 time for now */ #define XSCOM_IND_MAX_RETRIES 10 diff --git a/include/gx.h b/include/gx.h index f633892..4ba1661 100644 --- a/include/gx.h +++ b/include/gx.h @@ -24,30 +24,24 @@ /* P7 GX Mode 1 register (contains PSI BUID) */ #define GX_P7_MODE1_REG 0x0201180A -#define GX_P7_MODE1_PSI_BUID_MASK PPC_BITMASK(18,26) -#define GX_P7_MODE1_PSI_BUID_LSH PPC_BITLSHIFT(26) +#define GX_P7_MODE1_PSI_BUID PPC_BITMASK(18,26) #define GX_P7_MODE1_PSI_BUID_DISABLE PPC_BIT(27) /* P7+ GX Mode 4 register (PSI and NX BUIDs ) */ #define GX_P7P_MODE4_REG 0x02011811 #define GX_P7P_MODE4_ENABLE_NX_BUID PPC_BIT(0) -#define GX_P7P_MODE4_NX_BUID_BASE_MASK PPC_BITMASK(1,9) -#define GX_P7P_MODE4_NX_BUID_BASE_LSH PPC_BITLSHIFT(9) -#define GX_P7P_MODE4_NX_BUID_MASK_MASK PPC_BITMASK(10,18) -#define GX_P7P_MODE4_NX_BUID_MASK_LSH PPC_BITLSHIFT(18) -#define GX_P7P_MODE4_PSI_BUID_MASK PPC_BITMASK(19,27) -#define GX_P7P_MODE4_PSI_BUID_LSH PPC_BITLSHIFT(27) +#define GX_P7P_MODE4_NX_BUID_BASE PPC_BITMASK(1,9) +#define GX_P7P_MODE4_NX_BUID_MASK PPC_BITMASK(10,18) +#define GX_P7P_MODE4_PSI_BUID PPC_BITMASK(19,27) #define GX_P7P_MODE4_PSI_BUID_DISABLE PPC_BIT(28) /* P7 GX TCE BAR and mask */ #define GX_P7_GX0_TCE_BAR 0x02011845 -#define GX_P7_TCE_BAR_ADDR_MASK PPC_BITMASK(0,25) -#define GX_P7_TCE_BAR_ADDR_LSH PPC_BITLSHIFT(25) +#define GX_P7_TCE_BAR_ADDR PPC_BITMASK(0,25) #define GX_P7_TCE_BAR_ADDR_SHIFT PPC_BITLSHIFT(43) #define GX_P7_TCE_BAR_ENABLE PPC_BIT(26) #define GX_P7_GX0_TCE_MASK 0x0201184B -#define GX_P7_TCE_MASK_MASK PPC_BITMASK(0,25) -#define GX_P7_TCE_MASK_LSH PPC_BITLSHIFT(25) +#define GX_P7_TCE_MASK PPC_BITMASK(0,25) #define GX_P7_GX1_TCE_BAR 0x02011885 #define GX_P7_GX1_TCE_MASK 0x0201188B diff --git a/include/p5ioc2-regs.h b/include/p5ioc2-regs.h index 4cfd2e7..c4a63c6 100644 --- a/include/p5ioc2-regs.h +++ b/include/p5ioc2-regs.h @@ -65,10 +65,8 @@ #define P5IOC2_IBASE 0x0048 /* Interrupt base address */ #define P5IOC2_IRBM 0x00d8 /* Interrupt re-issue broadcast mask */ #define P5IOC2_SID 0x0038 /* P5IOC2 ID register */ -#define P5IOC2_SID_BUID_BASE_MASK PPC_BITMASK(14,22) -#define P5IOC2_SID_BUID_BASE_LSH PPC_BITLSHIFT(22) -#define P5IOC2_SID_BUID_MASK_MASK PPC_BITMASK(27,30) -#define P5IOC2_SID_BUID_MASK_LSH PPC_BITLSHIFT(30) +#define P5IOC2_SID_BUID_BASE PPC_BITMASK(14,22) +#define P5IOC2_SID_BUID_MASK PPC_BITMASK(27,30) #define P5IOC2_SBUID 0x00f8 /* P5IOC2 HUB BUID */ /* XIPM area */ @@ -90,17 +88,12 @@ #define CA_CCR 0x108 #define CA_DEVBUID 0x118 #define CA_DEVBUID_MASK PPC_BITMASK32(7,15) -#define CA_DEVBUID_LSH PPC_BITLSHIFT32(15) #define CA_TAR0 0x580 -#define CA_TAR_HUBID_MASK PPC_BITMASK(0,5) -#define CA_TAR_HUBID_LSH PPC_BITLSHIFT(5) -#define CA_TAR_ALTHUBID_MASK PPC_BITMASK(6,11) -#define CA_TAR_ALTHUBID_LSH PPC_BITLSHIFT(11) -#define CA_TAR_TCE_ADDR_MASK PPC_BITMASK(16,48) -#define CA_TAR_TCE_ADDR_LSH PPC_BITLSHIFT(48) +#define CA_TAR_HUBID PPC_BITMASK(0,5) +#define CA_TAR_ALTHUBID PPC_BITMASK(6,11) +#define CA_TAR_TCE_ADDR PPC_BITMASK(16,48) #define CA_TAR_VALID PPC_BIT(60) -#define CA_TAR_NUM_TCE_MASK PPC_BITMASK(61,63) -#define CA_TAR_NUM_TCE_LSH PPC_BITLSHIFT(63) +#define CA_TAR_NUM_TCE PPC_BITMASK(61,63) #define CA_TAR1 0x588 #define CA_TAR2 0x590 #define CA_TAR3 0x598 @@ -109,8 +102,7 @@ #define CA_PHBID0 0x650 #define CA_PHBID_PHB_ENABLE PPC_BIT32(0) #define CA_PHBID_ADDRSPACE_ENABLE PPC_BIT32(1) -#define CA_PHBID_PHB_TYPE_MASK PPC_BITMASK32(4,7) -#define CA_PHBID_PHB_TYPE_LSH PPC_BITLSHIFT32(7) +#define CA_PHBID_PHB_TYPE PPC_BITMASK32(4,7) #define CA_PHBTYPE_PCIX1_0 0 #define CA_PHBTYPE_PCIX2_0 1 #define CA_PHBTYPE_PCIE_G1 4 @@ -120,8 +112,7 @@ #define CA_PHBID_XBUS_64BIT PPC_BIT32(9) #define CA_PHBID_XBUS_266MHZ PPC_BIT32(10) /* PCI-E bits */ -#define CA_PHBID_EWIDTH_MASK PPC_BITMASK32(8,10) -#define CA_PHBID_EWIDTH_LSH PPC_BITLSHIFT32(10) +#define CA_PHBID_EWIDTH PPC_BITMASK32(8,10) #define CA_PHB_EWIDTH_X4 0 #define CA_PHB_EWIDTH_X8 1 #define CA_PHB_EWIDTH_X16 2 @@ -138,16 +129,13 @@ */ #define CAP_BUID 0x100 #define CAP_BUID_MASK PPC_BITMASK32(7,15) -#define CAP_BUID_LSH PPC_BITLSHIFT32(15) #define CAP_MSIBASE 0x108 /* Undocumented ! */ #define CAP_DMACSR 0x110 #define CAP_PLSSR 0x120 #define CAP_PCADR 0x140 #define CAP_PCADR_ENABLE PPC_BIT32(0) -#define CAP_PCADR_FUNC_MASK PPC_BITMASK32(21,23) -#define CAP_PCADR_FUNC_LSH PPC_BITLSHIFT32(23) -#define CAP_PCADR_EXTOFF_MASK PPC_BITLSHIFT32(4,7) -#define CAP_PCADR_EXTOFF_LSH PPC_BITLSHIFT32(7) +#define CAP_PCADR_FUNC PPC_BITMASK32(21,23) +#define CAP_PCADR_EXTOFF PPC_BITMASK32(4,7) #define CAP_PCDAT 0x130 #define CAP_PCFGRW 0x160 #define CAP_PCFGRW_ERR_RECOV_EN PPC_BIT32(1) @@ -177,17 +165,13 @@ #define CAP_CRR_RESET1 PPC_BIT32(0) #define CAP_CRR_RESET2 PPC_BIT32(1) #define CAP_XIVR0 0x400 -#define CAP_XIVR_PRIO_MASK 0x000000ff -#define CAP_XIVR_PRIO_LSH 0 -#define CAP_XIVR_SERVER_MASK 0x0000ff00 -#define CAP_XIVR_SERVER_LSH 8 +#define CAP_XIVR_PRIO 0x000000ff +#define CAP_XIVR_SERVER 0x0000ff00 #define CAP_XIVRn(n) (0x400 + ((n) << 4)) #define CAP_MVE0 0x500 #define CAP_MVE_VALID PPC_BIT32(0) -#define CAP_MVE_TBL_OFF_MASK PPC_BITMASK32(13,15) -#define CAP_MVE_TBL_OFF_LSH PPC_BITLSHIFT32(15) -#define CAP_MVE_NUM_INT_MASK PPC_BITMASK32(18,19) -#define CAP_MVE_NUM_INT_LSH PPC_BITLSHIFT32(19) +#define CAP_MVE_TBL_OFF PPC_BITMASK32(13,15) +#define CAP_MVE_NUM_INT PPC_BITMASK32(18,19) #define CAP_MVE1 0x510 #define CAP_MODE0 0x880 #define CAP_MODE1 0x890 @@ -198,13 +182,11 @@ * SHPC Registers */ #define SHPC_LOGICAL_SLOT 0xb40 -#define SHPC_LOGICAL_SLOT_STATE_MASK 0x00000002 -#define SHPC_LOGICAL_SLOT_STATE_LSH 0 +#define SHPC_LOGICAL_SLOT_STATE 0x00000003 #define SHPC_SLOT_STATE_POWER_ONLY 1 #define SHPC_SLOT_STATE_ENABLED 2 #define SHPC_SLOT_STATE_DISABLED 3 -#define SHPC_LOGICAL_SLOT_PRSNT_MASK 0x000000c00 -#define SHPC_LOGICAL_SLOT_PRSNT_LSH 10 +#define SHPC_LOGICAL_SLOT_PRSNT 0x000000c00 #define SHPC_SLOT_PRSTN_7_5W 0 #define SHPC_SLOT_PRSTN_25W 1 #define SHPC_SLOT_STATE_15W 2 diff --git a/include/p7ioc-regs.h b/include/p7ioc-regs.h index 2cd5b75..e868188 100644 --- a/include/p7ioc-regs.h +++ b/include/p7ioc-regs.h @@ -114,24 +114,18 @@ /* PHB Fundamental register set A */ #define PHB_BUID 0x100 -#define PHB_BUID_LSI_MASK PPC_BITMASK(7,15) -#define PHB_BUID_LSI_LSH PPC_BITLSHIFT(15) -#define PHB_BUID_MSI_MASK PPC_BITMASK(23,31) -#define PHB_BUID_MSI_LSH PPC_BITLSHIFT(31) +#define PHB_BUID_LSI PPC_BITMASK(7,15) +#define PHB_BUID_MSI PPC_BITMASK(23,31) #define PHB_DMA_CHAN_STATUS 0x110 #define PHB_CPU_LOADSTORE_STATUS 0x120 #define PHB_CONFIG_DATA 0x130 #define PHB_LOCK0 0x138 #define PHB_CONFIG_ADDRESS 0x140 #define PHB_CA_ENABLE PPC_BIT(0) -#define PHB_CA_BUS_MASK PPC_BITMASK(4,11) -#define PHB_CA_BUS_LSH PPC_BITLSHIFT(11) -#define PHB_CA_DEV_MASK PPC_BITMASK(12,16) -#define PHB_CA_DEV_LSH PPC_BITLSHIFT(16) -#define PHB_CA_FUNC_MASK PPC_BITMASK(17,19) -#define PHB_CA_FUNC_LSH PPC_BITLSHIFT(19) -#define PHB_CA_REG_MASK PPC_BITMASK(20,31) -#define PHB_CA_REG_LSH PPC_BITLSHIFT(31) +#define PHB_CA_BUS PPC_BITMASK(4,11) +#define PHB_CA_DEV PPC_BITMASK(12,16) +#define PHB_CA_FUNC PPC_BITMASK(17,19) +#define PHB_CA_REG PPC_BITMASK(20,31) #define PHB_LOCK1 0x148 #define PHB_PHB2_CONFIG 0x160 #define PHB_PHB2C_64B_TCE_EN PPC_BIT(2) @@ -148,14 +142,12 @@ #define PHB_M64_UPPER_BITS 0x1f0 #define PHB_TCE_KILL 0x210 #define PHB_TCEKILL_PAIR PPC_BIT(0) -#define PHB_TCEKILL_ADDR_MASK PPC_BITMASK(16,59) +#define PHB_TCEKILL_ADDR PPC_BITMASK(16,59) #define PHB_TCE_PREFETCH 0x218 #define PHB_IODA_ADDR 0x220 #define PHB_IODA_AD_AUTOINC PPC_BIT(0) -#define PHB_IODA_AD_TSEL_MASK PPC_BITMASK(11,15) -#define PHB_IODA_AD_TSEL_LSH PPC_BITLSHIFT(15) -#define PHB_IODA_AD_TADR_MASK PPC_BITMASK(48,63) -#define PHB_IODA_AD_TADR_LSH PPC_BITLSHIFT(63) +#define PHB_IODA_AD_TSEL PPC_BITMASK(11,15) +#define PHB_IODA_AD_TADR PPC_BITMASK(48,63) #define PHB_IODA_DATA0 0x228 #define PHB_IODA_DATA1 0x230 #define PHB_LOCK2 0x240 @@ -174,14 +166,10 @@ #define PHB_PAPR_ERR_INJ_CTL_FREEZE PPC_BIT(6) #define PHB_PAPR_ERR_INJ_ADDR 0x2b8 #define PHB_PAPR_ERR_INJ_MASK 0x2c0 -#define PHB_PAPR_ERR_INJ_MASK_CFG_MASK PPC_BITMASK(4,11) -#define PHB_PAPR_ERR_INJ_MASK_CFG_LSH PPC_BITLSHIFT(11) -#define PHB_PAPR_ERR_INJ_MASK_MMIO_MASK PPC_BITMASK(16,39) /* 16M aligned */ -#define PHB_PAPR_ERR_INJ_MASK_MMIO_LSH PPC_BITLSHIFT(39) -#define PHB_PAPR_ERR_INJ_MASK_IO_MASK PPC_BITMASK(16,47) /* 64K aligned */ -#define PHB_PAPR_ERR_INJ_MASK_IO_LSH PPC_BITLSHIFT(47) -#define PHB_PAPR_ERR_INJ_MASK_DMA_MASK PPC_BITMASK(60,63) /* 16 window */ -#define PHB_PAPR_ERR_INJ_MASK_DMA_LSH PPC_BITLSHIFT(63) +#define PHB_PAPR_ERR_INJ_MASK_CFG PPC_BITMASK(4,11) +#define PHB_PAPR_ERR_INJ_MASK_MMIO PPC_BITMASK(16,39) /* 16M aligned */ +#define PHB_PAPR_ERR_INJ_MASK_IO PPC_BITMASK(16,47) /* 64K aligned */ +#define PHB_PAPR_ERR_INJ_MASK_DMA PPC_BITMASK(60,63) /* 16 window */ #define PHB_ETU_ERR_SUMMARY 0x2c8 /* UTL registers */ @@ -235,10 +223,8 @@ #define PHB_PCIE_SLOTCTL2_PWR_EN_STAT PPC_BIT(17) #define PHB_PCIE_SLOTCTL2_RCK_EN_STAT PPC_BIT(18) #define PHB_PCIE_SLOTCTL2_PERST_STAT PPC_BIT(19) -#define PHB_PCIE_SLOTCTL2_PLED_S_MASK PPC_BITMASK(20,21) -#define PHB_PCIE_SLOTCTL2_PLED_S_LSH PPC_BITLSHIFT(21) /* use PCIE_INDIC_* */ -#define PHB_PCIE_SLOTCTL2_ALED_S_MASK PPC_BITMASK(22,23) -#define PHB_PCIE_SLOTCTL2_ALED_S_LSH PPC_BITLSHIFT(23) +#define PHB_PCIE_SLOTCTL2_PLED_S PPC_BITMASK(20,21) /* use PCIE_INDIC_* */ +#define PHB_PCIE_SLOTCTL2_ALED_S PPC_BITMASK(22,23) #define PHB_PCIE_SLOTCTL2_PRSTN_STAT PPC_BIT(24) #define PHB_PCIE_SLOTCTL2_PWRFLT_STAT PPC_BIT(25) #define PHB_PCIE_UTL_CONFIG 0x670 @@ -366,35 +352,24 @@ #define IODA_TBL_PEEV 20 /* L/M XIVT */ -#define IODA_XIVT_SERVER_MASK PPC_BITMASK(8,23) -#define IODA_XIVT_SERVER_LSH PPC_BITLSHIFT(23) -#define IODA_XIVT_PRIORITY_MASK PPC_BITMASK(24,31) -#define IODA_XIVT_PRIORITY_LSH PPC_BITLSHIFT(31) -#define IODA_XIVT_PENUM_MASK PPC_BITMASK(41,47) -#define IODA_XIVT_PENUM_LSH PPC_BITLSHIFT(47) -#define IODA_XIVT_HUBNUM_MASK PPC_BITMASK(58,59) -#define IODA_XIVT_HUBNUM_LSH PPC_BITLSHIFT(59) +#define IODA_XIVT_SERVER PPC_BITMASK(8,23) +#define IODA_XIVT_PRIORITY PPC_BITMASK(24,31) +#define IODA_XIVT_PENUM PPC_BITMASK(41,47) +#define IODA_XIVT_HUBNUM PPC_BITMASK(58,59) /* M64BT */ #define IODA_M64BT_ENABLE PPC_BIT(0) -#define IODA_M64BT_BASE_MASK PPC_BITMASK(8,31) -#define IODA_M64BT_BASE_LSH PPC_BITLSHIFT(31) -#define IODA_M64BT_MASK_MASK PPC_BITMASK(40,63) -#define IODA_M64BT_MASK_LSH PPC_BITLSHIFT(63) +#define IODA_M64BT_BASE PPC_BITMASK(8,31) +#define IODA_M64BT_MASK PPC_BITMASK(40,63) /* IODT/M32DT/M64DX */ -#define IODA_XXDT_PE_MASK PPC_BITMASK(0,6) -#define IODA_XXDT_PE_LSH PPC_BITLSHIFT(6) +#define IODA_XXDT_PE PPC_BITMASK(0,6) /* PELTM */ -#define IODA_PELTM_BUS_MASK PPC_BITMASK(0,7) -#define IODA_PELTM_BUS_LSH PPC_BITLSHIFT(7) -#define IODA_PELTM_DEV_MASK PPC_BITMASK(8,12) -#define IODA_PELTM_DEV_LSH PPC_BITLSHIFT(12) -#define IODA_PELTM_FUNC_MASK PPC_BITMASK(13,15) -#define IODA_PELTM_FUNC_LSH PPC_BITLSHIFT(15) -#define IODA_PELTM_BUS_VALID_MASK PPC_BITMASK(16,18) -#define IODA_PELTM_BUS_VALID_LSH PPC_BITLSHIFT(18) +#define IODA_PELTM_BUS PPC_BITMASK(0,7) +#define IODA_PELTM_DEV PPC_BITMASK(8,12) +#define IODA_PELTM_FUNC PPC_BITMASK(13,15) +#define IODA_PELTM_BUS_VALID PPC_BITMASK(16,18) #define IODA_BUS_VALID_ANY 0 #define IODA_BUS_VALID_3_BITS 2 #define IODA_BUS_VALID_4_BITS 3 @@ -406,49 +381,34 @@ #define IODA_PELTM_FUNC_VALID PPC_BIT(20) /* TVT */ -#define IODA_TVT0_TABLE_ADDR_MASK PPC_BITMASK(0,47) -#define IODA_TVT0_TABLE_ADDR_LSH PPC_BITLSHIFT(47) -#define IODA_TVT0_BUS_VALID_MASK PPC_BITMASK(48,50) -#define IODA_TVT0_BUS_VALID_LSH PPC_BITLSHIFT(50) -#define IODA_TVT0_TCE_TABLE_SIZE_MASK PPC_BITMASK(51,55) -#define IODA_TVT0_TCE_TABLE_SIZE_LSH PPC_BITLSHIFT(55) -#define IODA_TVT0_BUS_NUM_MASK PPC_BITMASK(56,63) -#define IODA_TVT0_BUS_NUM_LSH PPC_BITLSHIFT(63) +#define IODA_TVT0_TABLE_ADDR PPC_BITMASK(0,47) +#define IODA_TVT0_BUS_VALID PPC_BITMASK(48,50) +#define IODA_TVT0_TCE_TABLE_SIZE PPC_BITMASK(51,55) +#define IODA_TVT0_BUS_NUM PPC_BITMASK(56,63) #define IODA_TVT1_DEV_VALID PPC_BIT(2) -#define IODA_TVT1_DEV_NUM_MASK PPC_BITMASK(3,7) -#define IODA_TVT1_DEV_NUM_LSH PPC_BITLSHIFT(7) -#define IODA_TVT1_HUB_NUM_MASK PPC_BITMASK(10,11) -#define IODA_TVT1_HUB_NUM_LSH PPC_BITLSHIFT(11) +#define IODA_TVT1_DEV_NUM PPC_BITMASK(3,7) +#define IODA_TVT1_HUB_NUM PPC_BITMASK(10,11) #define IODA_TVT1_FUNC_VALID PPC_BIT(12) -#define IODA_TVT1_FUNC_NUM_MASK PPC_BITMASK(13,15) -#define IODA_TVT1_FUNC_NUM_LSH PPC_BITLSHIFT(15) -#define IODA_TVT1_IO_PSIZE_MASK PPC_BITMASK(19,23) -#define IODA_TVT1_IO_PSIZE_LSH PPC_BITLSHIFT(23) -#define IODA_TVT1_PE_NUM_MASK PPC_BITMASK(57,63) -#define IODA_TVT1_PE_NUM_LSH PPC_BITLSHIFT(63) +#define IODA_TVT1_FUNC_NUM PPC_BITMASK(13,15) +#define IODA_TVT1_IO_PSIZE PPC_BITMASK(19,23) +#define IODA_TVT1_PE_NUM PPC_BITMASK(57,63) /* MVT */ #define IODA_MVT_VALID PPC_BIT(0) -#define IODA_MVT_BUS_VALID_MASK PPC_BITMASK(21,23) -#define IODA_MVT_BUS_VALID_LSH PPC_BITLSHIFT(23) -#define IODA_MVT_BUS_NUM_MASK PPC_BITMASK(24,31) -#define IODA_MVT_BUS_NUM_LSH PPC_BITLSHIFT(31) -#define IODA_MVT_PE_NUM_MASK PPC_BITMASK(41,47) -#define IODA_MVT_PE_NUM_LSH PPC_BITLSHIFT(47) +#define IODA_MVT_BUS_VALID PPC_BITMASK(21,23) +#define IODA_MVT_BUS_NUM PPC_BITMASK(24,31) +#define IODA_MVT_PE_NUM PPC_BITMASK(41,47) #define IODA_MVT_DEV_VALID PPC_BIT(50) -#define IODA_MVT_DEV_NUM_MASK PPC_BITMASK(51,55) -#define IODA_MVT_DEV_NUM_LSH PPC_BITLSHIFT(55) +#define IODA_MVT_DEV_NUM PPC_BITMASK(51,55) #define IODA_MVT_FUNC_VALID PPC_BIT(60) -#define IODA_MVT_FUNC_NUM_MASK PPC_BITMASK(61,63) -#define IODA_MVT_FUNC_NUM_LSH PPC_BITLSHIFT(63) +#define IODA_MVT_FUNC_NUM PPC_BITMASK(61,63) /* PESTA */ #define IODA_PESTA_MMIO_FROZEN PPC_BIT(0) #define IODA_PESTA_MMIO_CAUSE PPC_BIT(2) #define IODA_PESTA_CFG_READ PPC_BIT(3) #define IODA_PESTA_CFG_WRITE PPC_BIT(4) -#define IODA_PESTA_TTYPE_MASK PPC_BITMASK(5,7) -#define IODA_PESTA_TTYPE_LSH PPC_BITLSHIFT(7) +#define IODA_PESTA_TTYPE PPC_BITMASK(5,7) #define PESTA_TTYPE_DMA_WRITE 0 #define PESTA_TTYPE_MSI 1 #define PESTA_TTYPE_DMA_READ 2 @@ -472,16 +432,12 @@ #define IODA_PESTA_TCE_ACCESS_FAULT PPC_BIT(19) #define IODA_PESTA_DMA_RESP_TIMEOUT PPC_BIT(20) #define IODA_PESTA_AIB_SIZE_INVALID PPC_BIT(21) -#define IODA_PESTA_LEM_BIT_MASK PPC_BITMASK(26,31) -#define IODA_PESTA_LEM_BIT_LSH PPC_BITLSHIFT(31) -#define IODA_PESTA_RID_MASK PPC_BITMASK(32,47) -#define IODA_PESTA_RID_LSH PPC_BITLSHIFT(47) -#define IODA_PESTA_MSI_DATA_MASK PPC_BITMASK(48,63) -#define IODA_PESTA_MSI_DATA_LSH PPC_BITLSHIFT(63) +#define IODA_PESTA_LEM_BIT PPC_BITMASK(26,31) +#define IODA_PESTA_RID PPC_BITMASK(32,47) +#define IODA_PESTA_MSI_DATA PPC_BITMASK(48,63) /* PESTB */ #define IODA_PESTB_DMA_STOPPED PPC_BIT(0) -#define IODA_PESTB_FAIL_ADDR_MASK PPC_BITMASK(3,63) -#define IODA_PESTB_FAIL_ADDR_LSH PPC_BITLSHIFT(63) +#define IODA_PESTB_FAIL_ADDR PPC_BITMASK(3,63) #endif /* __P7IOC_REGS_H */ diff --git a/include/pci-cfg.h b/include/pci-cfg.h index 7c98f3f..c705d25 100644 --- a/include/pci-cfg.h +++ b/include/pci-cfg.h @@ -46,7 +46,7 @@ #define PCI_CFG_HDR_TYPE 0x000e #define PCI_CFG_BIST 0x000f #define PCI_CFG_BAR0 0x0010 -#define PCI_CFG_BAR_TYPE_MASK 0x00000001 +#define PCI_CFG_BAR_TYPE 0x00000001 #define PCI_CFG_BAR_TYPE_MEM 0x00000000 #define PCI_CFG_BAR_TYPE_IO 0x00000001 #define PCI_CFG_BAR_MEM64 0x00000004 @@ -117,10 +117,8 @@ #define PCI_CFG_CAP_ID_EXP 0x10 /* PCI Express capability fields */ #define PCICAP_EXP_CAPABILITY_REG 0x02 -#define PCICAP_EXP_CAP_VERSION_MASK 0x000f -#define PCICAP_EXP_CAP_VERSION_LSH 0 -#define PCICAP_EXP_CAP_TYPE_MASK 0x00f0 -#define PCICAP_EXP_CAP_TYPE_LSH 4 +#define PCICAP_EXP_CAP_VERSION 0x000f +#define PCICAP_EXP_CAP_TYPE 0x00f0 #define PCIE_TYPE_ENDPOINT 0x0 #define PCIE_TYPE_LEGACY 0x1 #define PCIE_TYPE_ROOT_PORT 0x4 @@ -131,27 +129,23 @@ #define PCIE_TYPE_RC_INTEGRATED 0x9 #define PCIE_TYPE_RC_EVT_COLL 0xa #define PCICAP_EXP_CAP_SLOT 0x0100 -#define PCICAP_EXP_CAP_MSI_NUM_MASK 0x3e00 -#define PCICAP_EXP_CAP_MSI_NUM_LSH 9 +#define PCICAP_EXP_CAP_MSI_NUM 0x3e00 #define PCICAP_EXP_CAP_TCS_ROUTING 0x4000 #define PCICAP_EXP_DEVCAP 0x04 -#define PCICAP_EXP_DEVCAP_MPSS_MASK 0x00000007 -#define PCICAP_EXP_DEVCAP_MPSS_LSH 0 +#define PCICAP_EXP_DEVCAP_MPSS 0x00000007 #define PCIE_MPSS_128 0 #define PCIE_MPSS_256 1 #define PCIE_MPSS_512 2 #define PCIE_MPSS_1024 3 #define PCIE_MPSS_2048 4 #define PCIE_MPSS_4096 5 -#define PCICAP_EXP_DEVCAP_PHANT_MASK 0x00000018 -#define PCICAP_EXP_DEVCAP_PHANT_LSH 3 +#define PCICAP_EXP_DEVCAP_PHANT 0x00000018 #define PCIE_PHANTOM_NONE 0 #define PCIE_PHANTOM_1MSB 1 #define PCIE_PHANTOM_2MSB 2 #define PCIE_PHANTOM_3MSB 3 #define PCICAP_EXP_DEVCAP_EXTTAG 0x00000020 -#define PCICAP_EXP_DEVCAP_L0SL_MASK 0x000001c0 -#define PCICAP_EXP_DEVCAP_L0SL_LSH 6 +#define PCICAP_EXP_DEVCAP_L0SL 0x000001c0 #define PCIE_L0SL_MAX_64NS 0 #define PCIE_L0SL_MAX_128NS 1 #define PCIE_L0SL_MAX_256NS 2 @@ -160,8 +154,7 @@ #define PCIE_L0SL_MAX_2US 5 #define PCIE_L0SL_MAX_4US 6 #define PCIE_L0SL_MAX_NO_LIMIT 7 -#define PCICAP_EXP_DEVCAP_L1L_MASK 0x00000e00 -#define PCICAP_EXP_DEVCAP_L1L_LSH 9 +#define PCICAP_EXP_DEVCAP_L1L 0x00000e00 #define PCIE_L1L_MAX_1US 0 #define PCIE_L1L_MAX_2US 1 #define PCIE_L1L_MAX_4US 2 @@ -171,10 +164,8 @@ #define PCIE_L1L_MAX_64US 6 #define PCIE_L1L_MAX_NO_LIMIT 7 #define PCICAP_EXP_ROLE_BASED_ERR 0x00008000 -#define PCICAP_EXP_DEVCAP_PWRVAL_MASK 0x03fc0000 -#define PCICAP_EXP_DEVCAP_PWRVAL_LSH 18 -#define PCICAP_EXP_DEVCAP_PWRSCA_MASK 0x0c000000 -#define PCICAP_EXP_DEVCAP_PWRSCA_LSH 26 +#define PCICAP_EXP_DEVCAP_PWRVAL 0x03fc0000 +#define PCICAP_EXP_DEVCAP_PWRSCA 0x0c000000 #define PCIE_SLOT_PWR_SCALE_1x 0 #define PCIE_SLOT_PWR_SCALE_0d1x 1 #define PCIE_SLOT_PWR_SCALE_0d01x 2 @@ -186,8 +177,7 @@ #define PCICAP_EXP_DEVCTL_FE_REPORT 0x0004 #define PCICAP_EXP_DEVCTL_UR_REPORT 0x0008 #define PCICAP_EXP_DEVCTL_RELAX_ORD 0x0010 -#define PCICAP_EXP_DEVCTL_MPS_MASK 0x00e0 -#define PCICAP_EXP_DEVCTL_MPS_LSH 5 +#define PCICAP_EXP_DEVCTL_MPS 0x00e0 #define PCIE_MPS_128B 0 #define PCIE_MPS_256B 1 #define PCIE_MPS_512B 2 @@ -198,8 +188,7 @@ #define PCICAP_EXP_DEVCTL_PHANTOM 0x0200 #define PCICAP_EXP_DEVCTL_AUX_POW_PM 0x0400 #define PCICAP_EXP_DEVCTL_NO_SNOOP 0x0800 -#define PCICAP_EXP_DEVCTL_MRRS_MASK 0x7000 -#define PCICAP_EXP_DEVCTL_MRRS_LSH 12 +#define PCICAP_EXP_DEVCTL_MRRS 0x7000 #define PCIE_MRSS_128B 0 #define PCIE_MRSS_256B 1 #define PCIE_MRSS_512B 2 @@ -216,8 +205,7 @@ #define PCICAP_EXP_DEVSTAT_AUX_POW 0x0010 #define PCICAP_EXP_DEVSTAT_TPEND 0x0020 #define PCICAP_EXP_LCAP 0x0c -#define PCICAP_EXP_LCAP_MAXSPD_MASK 0x0000000f -#define PCICAP_EXP_LCAP_MAXSPD_LSH 0 +#define PCICAP_EXP_LCAP_MAXSPD 0x0000000f #define PCIE_LSPEED_VECBIT_0 0x1 #define PCIE_LSPEED_VECBIT_1 0x2 #define PCIE_LSPEED_VECBIT_2 0x3 @@ -225,8 +213,7 @@ #define PCIE_LSPEED_VECBIT_4 0x5 #define PCIE_LSPEED_VECBIT_5 0x6 #define PCIE_LSPEED_VECBIT_6 0x7 -#define PCICAP_EXP_LCAP_MAXWDTH_MASK 0x000003f0 -#define PCICAP_EXP_LCAP_MAXWDTH_LSH 4 +#define PCICAP_EXP_LCAP_MAXWDTH 0x000003f0 #define PCIE_LWIDTH_1X 1 #define PCIE_LWIDTH_2X 2 #define PCIE_LWIDTH_4X 4 @@ -236,8 +223,7 @@ #define PCIE_LWIDTH_32X 32 #define PCICAP_EXP_LCAP_ASPM_L0S 0x00000400 #define PCICAP_EXP_LCAP_ASPM_L1 0x00000800 -#define PCICAP_EXP_LCAP_L0S_EXLT_MASK 0x00007000 -#define PCICAP_EXP_LCAP_L0S_EXLT_LSH 12 +#define PCICAP_EXP_LCAP_L0S_EXLT 0x00007000 #define PCIE_L0S_EXLT_LESS_64NS 0 #define PCIE_L0S_EXLT_64NS_128NS 1 #define PCIE_L0S_EXLT_128NS_256NS 2 @@ -246,8 +232,7 @@ #define PCIE_L0S_EXLT_1US_2US 5 #define PCIE_L0S_EXLT_2US_4US 6 #define PCIE_L0S_EXLT_MORE_4US 7 -#define PCICAP_EXP_LCAP_L1_EXLT_MASK 0x00038000 -#define PCICAP_EXP_LCAP_L1_EXLT_LSH 15 +#define PCICAP_EXP_LCAP_L1_EXLT 0x00038000 #define PCIE_L1_EXLT_LESS_1US 0 #define PCIE_L1_EXLT_1US_2US 1 #define PCIE_L1_EXLT_2US_4US 2 @@ -261,8 +246,7 @@ #define PCICAP_EXP_LCAP_DL_ACT_REP 0x00100000 #define PCICAP_EXP_LCAP_LNKBWDTH_NOTF 0x00200000 #define PCICAP_EXP_LCAP_ASPM_OPT_CMPL 0x00400000 -#define PCICAP_EXP_LCAP_PORTNUM_MASK 0xff000000 -#define PCICAP_EXP_LCAP_PORTNUM_LSH 24 +#define PCICAP_EXP_LCAP_PORTNUM 0xff000000 #define PCICAP_EXP_LCTL 0x10 #define PCICAP_EXP_LCTL_ASPM_L0S 0x0001 #define PCICAP_EXP_LCTL_ASPM_L1 0x0002 @@ -276,10 +260,8 @@ #define PCICAP_EXP_LCTL_LBWM_INT_EN 0x0400 #define PCICAP_EXP_LCTL_LAWD_INT_EN 0x0800 #define PCICAP_EXP_LSTAT 0x12 -#define PCICAP_EXP_LSTAT_SPEED_MASK 0x000f -#define PCICAP_EXP_LSTAT_SPEED_LSH 0 /* use PCIE_LSPEED_* consts */ -#define PCICAP_EXP_LSTAT_WIDTH_MASK 0x03f0 -#define PCICAP_EXP_LSTAT_WIDTH_LSH 4 /* use PCIE_LWIDTH_* consts */ +#define PCICAP_EXP_LSTAT_SPEED 0x000f /* use PCIE_LSPEED_* consts */ +#define PCICAP_EXP_LSTAT_WIDTH 0x03f0 /* use PCIE_LWIDTH_* consts */ #define PCICAP_EXP_LSTAT_TRAINING 0x0800 #define PCICAP_EXP_LSTAT_SLOTCLKCFG 0x1000 #define PCICAP_EXP_LSTAT_DLLL_ACT 0x2000 @@ -293,14 +275,11 @@ #define PCICAP_EXP_SLOTCAP_PWRI 0x00000010 #define PCICAP_EXP_SLOTCAP_HPLUG_SURP 0x00000020 #define PCICAP_EXP_SLOTCAP_HPLUG_CAP 0x00000040 -#define PCICAP_EXP_SLOTCAP_SPLVA_MASK 0x00007f80 -#define PCICAP_EXP_SLOTCAP_SPLLVA_LSH 7 -#define PCICAP_EXP_SLOTCAP_SPLSC_MASK 0x00018000 -#define PCICAP_EXP_SLOTCAP_SPLSC_LSH 15 +#define PCICAP_EXP_SLOTCAP_SPLVA 0x00007f80 +#define PCICAP_EXP_SLOTCAP_SPLSC 0x00018000 #define PCICAP_EXP_SLOTCAP_EIP 0x00020000 #define PCICAP_EXP_SLOTCAP_NO_CMDCOMP 0x00040000 -#define PCICAP_EXP_SLOTCAP_PSLOT_MASK 0xfff80000 -#define PCICAP_EXP_SLOTCAP_PSLOT_LSH 19 +#define PCICAP_EXP_SLOTCAP_PSLOT 0xfff80000 #define PCICAP_EXP_SLOTCTL 0x18 #define PCICAP_EXP_SLOTCTL_ATTNB 0x0001 #define PCICAP_EXP_SLOTCTL_PFLT 0x0002 @@ -308,13 +287,11 @@ #define PCICAP_EXP_SLOTCTL_PDETECT 0x0008 #define PCICAP_EXP_SLOTCTL_CMDCOMPINT 0x0010 #define PCICAP_EXP_SLOTCTL_HPINT 0x0020 -#define PCICAP_EXP_SLOTCTL_ATTNI_MASK 0x00c0 -#define PCICAP_EXP_SLOTCTL_ATTNI_LSH 6 +#define PCICAP_EXP_SLOTCTL_ATTNI 0x00c0 #define PCIE_INDIC_ON 1 #define PCIE_INDIC_BLINK 2 #define PCIE_INDIC_OFF 3 -#define PCICAP_EXP_SLOTCTL_PWRI_MASK 0x0300 -#define PCICAP_EXP_SLOTCTL_PWRI_LSH 8 /* Use PCIE_INDIC_* consts */ +#define PCICAP_EXP_SLOTCTL_PWRI 0x0300 /* Use PCIE_INDIC_* consts */ #define PCICAP_EXP_SLOTCTL_PWRCTLR 0x0400 #define PCICAP_EXP_SLOTCTL_EIC 0x0800 #define PCICAP_EXP_SLOTCTL_DLLSTCHG 0x1000 @@ -337,13 +314,11 @@ #define PCICAP_EXP_RCAP 0x1e #define PCICAP_EXP_RCAP_CRS_VISIBLE 0x0001 #define PCICAP_EXP_RSTAT 0x20 -#define PCICAP_EXP_RSTAT_PME_RID_MASK 0x0000ffff -#define PCICAP_EXP_RSTAT_PME_RID_LSH 0 +#define PCICAP_EXP_RSTAT_PME_RID 0x0000ffff #define PCICAP_EXP_RSTAT_PME_STATUS 0x00010000 #define PCICAP_EXP_RSTAT_PME_PENDING 0x00020000 #define PCIECAP_EXP_DCAP2 0x24 -#define PCICAP_EXP_DCAP2_CMPTOUT_MASK 0x0000000f -#define PCICAP_EXP_DCAP2_CMPTOUT_LSH 0 +#define PCICAP_EXP_DCAP2_CMPTOUT 0x0000000f #define PCICAP_EXP_DCAP2_CMPTOUT_DIS 0x00000010 #define PCICAP_EXP_DCAP2_ARI_FWD 0x00000020 #define PCICAP_EXP_DCAP2_ATOMIC_RTE 0x00000040 @@ -358,15 +333,13 @@ #define PCICAP_EXP_DCAP2_OBFF_WAKE 0x00080000 #define PCICAP_EXP_DCAP2_EXTFMT 0x00100000 #define PCICAP_EXP_DCAP2_EETLP_PFX 0x00200000 -#define PCICAP_EXP_DCAP2_MAXEETP_MASK 0x00c00000 -#define PCICAP_EXP_DCAP2_MAXEETP_LSH 22 +#define PCICAP_EXP_DCAP2_MAXEETP 0x00c00000 #define PCIE_EETLPP_1 1 #define PCIE_EETLPP_2 2 #define PCIE_EETLPP_3 3 #define PCIE_EETLPP_4 0 #define PCICAP_EXP_DCTL2 0x28 -#define PCICAP_EXP_DCTL2_CMPTOUT_MASK 0x000f -#define PCICAP_EXP_DCTL2_CMPTOUT_LSH 0 +#define PCICAP_EXP_DCTL2_CMPTOUT 0x000f #define PCICAP_EXP_DCTL2_CMPTOUT_DIS 0x0010 #define PCICAP_EXP_DCTL2_ARI_FWD 0x0020 #define PCICAP_EXP_DCTL2_ATOMIC_REQ 0x0040 @@ -374,8 +347,7 @@ #define PCICAP_EXP_DCTL2_IDO_REQ 0x0100 #define PCICAP_EXP_DCTL2_IDO_COMPL 0x0200 #define PCICAP_EXP_DCTL2_LTR 0x0400 -#define PCICAP_EXP_DCTL2_OBFF_MASK 0x6000 -#define PCICAP_EXP_DCTL2_OBFF_LSH 13 +#define PCICAP_EXP_DCTL2_OBFF 0x6000 #define PCIE_OBFF_MODE_DISABLED 0 #define PCIE_OBFF_MODE_MSG_A 1 #define PCIE_OBFF_MODE_MSG_B 2 @@ -388,17 +360,14 @@ #define PCICAP_EXP_LCAP2_SP_8d0GTs 0x00000008 #define PCICAP_EXP_LCAP2_XLINK 0x00000100 #define PCICAP_EXP_LCTL2 0x30 -#define PCICAP_EXP_LCTL2_TLSPD_MASK 0x000f -#define PCICAP_EXP_LCTL2_TLSPD_LSH 0 /* use PCIE_LSPEED_ consts */ +#define PCICAP_EXP_LCTL2_TLSPD 0x000f /* use PCIE_LSPEED_ consts */ #define PCICAP_EXP_LCTL2_ENTER_COMPL 0x0010 #define PCICAP_EXP_LCTL2_HWAUTSPDIS 0x0020 #define PCICAP_EXP_LCTL2_SEL_DEEMPH 0x0040 -#define PCICAP_EXP_LCTL2_XMTMARG_MASK 0x0380 -#define PCICAP_EXP_LCTL2_XMTMARG_LSH 7 +#define PCICAP_EXP_LCTL2_XMTMARG 0x0380 #define PCICAP_EXP_LCTL2_ENTER_MCOMPL 0x0400 #define PCICAP_EXP_LCTL2_COMPL_SOS 0x0800 -#define PCICAP_EXP_LCTL2_CMPPDEM_MASK 0xf000 -#define PCICAP_EXP_LCTL2_CMPPDEM_LSH 12 +#define PCICAP_EXP_LCTL2_CMPPDEM 0xf000 #define PCICAP_EXP_LSTA2 0x32 #define PCICAP_EXP_LSTA2_DEMPH_LVL 0x0001 #define PCICAP_EXP_LSTA2_EQ_COMPLETE 0x0002 @@ -414,12 +383,9 @@ * PCI-E Extended capabilties */ #define PCI_CFG_ECAP_START 0x100 -#define PCI_CFG_ECAP_ID_MASK 0x0000ffff -#define PCI_CFG_ECAP_ID_LSH 0 -#define PCI_CFG_ECAP_VERS_MASK 0x000f0000 -#define PCI_CFG_ECAP_VERS_LSH 16 -#define PCI_CFG_ECAP_NEXT_MASK 0xfff00000 -#define PCI_CFG_ECAP_NEXT_LSH 20 +#define PCI_CFG_ECAP_ID 0x0000ffff +#define PCI_CFG_ECAP_VERS 0x000f0000 +#define PCI_CFG_ECAP_NEXT 0xfff00000 /* AER Ext. Capability */ #define PCIECAP_ID_AER 0x0001 @@ -484,8 +450,7 @@ #define PCIECAP_AER_CE_MASK_CORTD_INTERNAL 0x00004000 #define PCIECAP_AER_CE_MASK_HDR_LOG_OVFL 0x00008000 #define PCIECAP_AER_CAPCTL 0x18 -#define PCIECAP_AER_CAPCTL_FPTR_MASK 0x0000001f -#define PCIECAP_AER_CAPCTL_FPTR_LSH 0 +#define PCIECAP_AER_CAPCTL_FPTR 0x0000001f #define PCIECAP_AER_CAPCTL_ECRCG_CAP 0x00000020 #define PCIECAP_AER_CAPCTL_ECRCG_EN 0x00000040 #define PCIECAP_AER_CAPCTL_ECRCC_CAP 0x00000080 @@ -509,13 +474,10 @@ #define PCIECAP_AER_RERR_F_UFATAL 0x00000010 #define PCIECAP_AER_RERR_NFE 0x00000020 #define PCIECAP_AER_RERR_FE 0x00000040 -#define PCIECAP_AER_RERR_MSINO_MASK 0xf8000000 -#define PCIECAP_AER_RERR_MSINO_LSH 27 +#define PCIECAP_AER_RERR_MSINO 0xf8000000 #define PCIECAP_AER_SRCID 0x34 -#define PCIECAP_AER_SRCID_CORR_MASK 0x0000ffff -#define PCIECAP_AER_SRCID_CORR_LSH 0 -#define PCIECAP_AER_SRCID_FNF_MASK 0xffff0000 -#define PCIECAP_AER_SRCID_FNF_LSH 16 +#define PCIECAP_AER_SRCID_CORR 0x0000ffff +#define PCIECAP_AER_SRCID_FNF 0xffff0000 #define PCIECAP_AER_TLP_PFX_LOG0 0x38 #define PCIECAP_AER_TLP_PFX_LOG1 0x3c #define PCIECAP_AER_TLP_PFX_LOG2 0x40 diff --git a/include/phb3-regs.h b/include/phb3-regs.h index 686a113..144c344 100644 --- a/include/phb3-regs.h +++ b/include/phb3-regs.h @@ -24,8 +24,7 @@ /* PHB Fundamental register set A */ #define PHB_LSI_SOURCE_ID 0x100 -#define PHB_LSI_SRC_ID_MASK PPC_BITMASK(5,12) -#define PHB_LSI_SRC_ID_LSH PPC_BITLSHIFT(12) +#define PHB_LSI_SRC_ID PPC_BITMASK(5,12) #define PHB_DMA_CHAN_STATUS 0x110 #define PHB_DMA_CHAN_ANY_ERR PPC_BIT(27) #define PHB_DMA_CHAN_ANY_ERR1 PPC_BIT(28) @@ -36,33 +35,24 @@ #define PHB_CPU_LS_ANY_FREEZE PPC_BIT(29) #define PHB_DMA_MSI_NODE_ID 0x128 #define PHB_DMAMSI_NID_FIXED PPC_BIT(0) -#define PHB_DMAMSI_NID_MASK PPC_BITMASK(24,31) -#define PHB_DMAMSI_NID_LSH PPC_BITLSHIFT(31) +#define PHB_DMAMSI_NID PPC_BITMASK(24,31) #define PHB_CONFIG_DATA 0x130 #define PHB_LOCK0 0x138 #define PHB_CONFIG_ADDRESS 0x140 #define PHB_CA_ENABLE PPC_BIT(0) -#define PHB_CA_BUS_MASK PPC_BITMASK(4,11) -#define PHB_CA_BUS_LSH PPC_BITLSHIFT(11) -#define PHB_CA_DEV_MASK PPC_BITMASK(12,16) -#define PHB_CA_DEV_LSH PPC_BITLSHIFT(16) -#define PHB_CA_FUNC_MASK PPC_BITMASK(17,19) -#define PHB_CA_FUNC_LSH PPC_BITLSHIFT(19) -#define PHB_CA_REG_MASK PPC_BITMASK(20,31) -#define PHB_CA_REG_LSH PPC_BITLSHIFT(31) -#define PHB_CA_PE_MASK PPC_BITMASK(40,47) -#define PHB_CA_PE_LSH PPC_BITLSHIFT(47) +#define PHB_CA_BUS PPC_BITMASK(4,11) +#define PHB_CA_DEV PPC_BITMASK(12,16) +#define PHB_CA_FUNC PPC_BITMASK(17,19) +#define PHB_CA_REG PPC_BITMASK(20,31) +#define PHB_CA_PE PPC_BITMASK(40,47) #define PHB_LOCK1 0x148 #define PHB_IVT_BAR 0x150 #define PHB_IVT_BAR_ENABLE PPC_BIT(0) -#define PHB_IVT_BASE_ADDRESS_MASK PPC_BITMASK(14,48) -#define PHB_IVT_BASE_ADDRESS_LSH PPC_BITLSHIFT(48) -#define PHB_IVT_LENGTH_MASK PPC_BITMASK(52,63) -#define PHB_IVT_LENGTH_ADDRESS_LSH PPC_BITLSHIFT(63) +#define PHB_IVT_BASE_ADDRESS PPC_BITMASK(14,48) +#define PHB_IVT_LENGTH PPC_BITMASK(52,63) #define PHB_RBA_BAR 0x158 #define PHB_RBA_BAR_ENABLE PPC_BIT(0) -#define PHB_RBA_BASE_ADDRESS_MASK PPC_BITMASK(14,55) -#define PHB_RBA_BASE_ADDRESS_LSH PPC_BITLSHIFT(55) +#define PHB_RBA_BASE_ADDRESS PPC_BITMASK(14,55) #define PHB_PHB3_CONFIG 0x160 #define PHB_PHB3C_64B_TCE_EN PPC_BIT(2) #define PHB_PHB3C_32BIT_MSI_EN PPC_BIT(8) @@ -70,40 +60,33 @@ #define PHB_PHB3C_M32_EN PPC_BIT(16) #define PHB_RTT_BAR 0x168 #define PHB_RTT_BAR_ENABLE PPC_BIT(0) -#define PHB_RTT_BASE_ADDRESS_MASK PPC_BITMASK(14,46) -#define PHB_RTT_BASE_ADDRESS_LSH PPC_BITLSHIFT(46) +#define PHB_RTT_BASE_ADDRESS PPC_BITMASK(14,46) #define PHB_PELTV_BAR 0x188 #define PHB_PELTV_BAR_ENABLE PPC_BIT(0) -#define PHB_PELTV_BASE_ADDRESS_MASK PPC_BITMASK(14,50) -#define PHB_PELTV_BASE_ADDRESS_LSH PPC_BITLSHIFT(50) +#define PHB_PELTV_BASE_ADDRESS PPC_BITMASK(14,50) #define PHB_M32_BASE_ADDR 0x190 #define PHB_M32_BASE_MASK 0x198 #define PHB_M32_START_ADDR 0x1a0 #define PHB_PEST_BAR 0x1a8 #define PHB_PEST_BAR_ENABLE PPC_BIT(0) -#define PHB_PEST_BASE_ADDRESS_MASK PPC_BITMASK(14,51) -#define PHB_PEST_BASE_ADDRESS_LSH PPC_BITLSHIFT(51) +#define PHB_PEST_BASE_ADDRESS PPC_BITMASK(14,51) #define PHB_M64_UPPER_BITS 0x1f0 #define PHB_INTREP_TIMER 0x1f8 #define PHB_DMARD_SYNC 0x200 #define PHB_RTC_INVALIDATE 0x208 #define PHB_RTC_INVALIDATE_ALL PPC_BIT(0) -#define PHB_RTC_INVALIDATE_RID_MASK PPC_BITMASK(16,31) -#define PHB_RTC_INVALIDATE_RID_LSH PPC_BITLSHIFT(31) +#define PHB_RTC_INVALIDATE_RID PPC_BITMASK(16,31) #define PHB_TCE_KILL 0x210 #define PHB_TCE_KILL_ALL PPC_BIT(0) #define PHB_TCE_SPEC_CTL 0x218 #define PHB_IODA_ADDR 0x220 #define PHB_IODA_AD_AUTOINC PPC_BIT(0) -#define PHB_IODA_AD_TSEL_MASK PPC_BITMASK(11,15) -#define PHB_IODA_AD_TSEL_LSH PPC_BITLSHIFT(15) -#define PHB_IODA_AD_TADR_MASK PPC_BITMASK(55,63) -#define PHB_IODA_AD_TADR_LSH PPC_BITLSHIFT(63) +#define PHB_IODA_AD_TSEL PPC_BITMASK(11,15) +#define PHB_IODA_AD_TADR PPC_BITMASK(55,63) #define PHB_IODA_DATA0 0x228 #define PHB_FFI_REQUEST 0x238 #define PHB_FFI_LOCK_CLEAR PPC_BIT(3) -#define PHB_FFI_REQUEST_ISN_MASK PPC_BITMASK(49,59) -#define PHB_FFI_REQUEST_ISN_LSH PPC_BITLSHIFT(59) +#define PHB_FFI_REQUEST_ISN PPC_BITMASK(49,59) #define PHB_FFI_LOCK 0x240 #define PHB_XIVE_UPDATE 0x248 /* Broken in DD1 */ #define PHB_PHB3_GEN_CAP 0x250 @@ -112,8 +95,7 @@ #define PHB_PHB3_EEH_CAP 0x268 #define PHB_IVC_INVALIDATE 0x2a0 #define PHB_IVC_INVALIDATE_ALL PPC_BIT(0) -#define PHB_IVC_INVALIDATE_SID_MASK PPC_BITMASK(16,31) -#define PHB_IVC_INVALIDATE_SID_LSH PPC_BITLSHIFT(31) +#define PHB_IVC_INVALIDATE_SID PPC_BITMASK(16,31) #define PHB_IVC_UPDATE 0x2a8 #define PHB_IVC_UPDATE_ENABLE_P PPC_BIT(0) #define PHB_IVC_UPDATE_ENABLE_Q PPC_BIT(1) @@ -121,20 +103,13 @@ #define PHB_IVC_UPDATE_ENABLE_PRI PPC_BIT(3) #define PHB_IVC_UPDATE_ENABLE_GEN PPC_BIT(4) #define PHB_IVC_UPDATE_ENABLE_CON PPC_BIT(5) -#define PHB_IVC_UPDATE_GEN_MATCH_MASK PPC_BITMASK(6, 7) -#define PHB_IVC_UPDATE_GEN_MATCH_LSH PPC_BITLSHIFT(7) -#define PHB_IVC_UPDATE_SERVER_MASK PPC_BITMASK(8, 23) -#define PHB_IVC_UPDATE_SERVER_LSH PPC_BITLSHIFT(23) -#define PHB_IVC_UPDATE_PRI_MASK PPC_BITMASK(24, 31) -#define PHB_IVC_UPDATE_PRI_LSH PPC_BITLSHIFT(31) -#define PHB_IVC_UPDATE_GEN_MASK PPC_BITMASK(32,33) -#define PHB_IVC_UPDATE_GEN_LSH PPC_BITLSHIFT(33) -#define PHB_IVC_UPDATE_P_MASK PPC_BITMASK(34,34) -#define PHB_IVC_UPDATE_P_LSH PPC_BITLSHIFT(34) -#define PHB_IVC_UPDATE_Q_MASK PPC_BITMASK(35,35) -#define PHB_IVC_UPDATE_Q_LSH PPC_BITLSHIFT(35) -#define PHB_IVC_UPDATE_SID_MASK PPC_BITMASK(48,63) -#define PHB_IVC_UPDATE_SID_LSH PPC_BITLSHIFT(63) +#define PHB_IVC_UPDATE_GEN_MATCH PPC_BITMASK(6, 7) +#define PHB_IVC_UPDATE_SERVER PPC_BITMASK(8, 23) +#define PHB_IVC_UPDATE_PRI PPC_BITMASK(24, 31) +#define PHB_IVC_UPDATE_GEN PPC_BITMASK(32,33) +#define PHB_IVC_UPDATE_P PPC_BITMASK(34,34) +#define PHB_IVC_UPDATE_Q PPC_BITMASK(35,35) +#define PHB_IVC_UPDATE_SID PPC_BITMASK(48,63) #define PHB_PAPR_ERR_INJ_CTL 0x2b0 #define PHB_PAPR_ERR_INJ_CTL_INB PPC_BIT(0) #define PHB_PAPR_ERR_INJ_CTL_OUTB PPC_BIT(1) @@ -144,13 +119,10 @@ #define PHB_PAPR_ERR_INJ_CTL_WR PPC_BIT(5) #define PHB_PAPR_ERR_INJ_CTL_FREEZE PPC_BIT(6) #define PHB_PAPR_ERR_INJ_ADDR 0x2b8 -#define PHB_PAPR_ERR_INJ_ADDR_MMIO_MASK PPC_BITMASK(16,63) -#define PHB_PAPR_ERR_INJ_ADDR_MMIO_LSH PPC_BITLSHIFT(63) +#define PHB_PAPR_ERR_INJ_ADDR_MMIO PPC_BITMASK(16,63) #define PHB_PAPR_ERR_INJ_MASK 0x2c0 -#define PHB_PAPR_ERR_INJ_MASK_CFG_MASK PPC_BITMASK(4,11) -#define PHB_PAPR_ERR_INJ_MASK_CFG_LSH PPC_BITLSHIFT(11) -#define PHB_PAPR_ERR_INJ_MASK_MMIO_MASK PPC_BITMASK(16,63) -#define PHB_PAPR_ERR_INJ_MASK_MMIO_LSH PPC_BITLSHIFT(63) +#define PHB_PAPR_ERR_INJ_MASK_CFG PPC_BITMASK(4,11) +#define PHB_PAPR_ERR_INJ_MASK_MMIO PPC_BITMASK(16,63) #define PHB_ETU_ERR_SUMMARY 0x2c8 /* UTL registers */ @@ -340,39 +312,27 @@ #define IODA2_TBL_PEEV 20 /* LXIVT */ -#define IODA2_LXIVT_SERVER_MASK PPC_BITMASK(8,23) -#define IODA2_LXIVT_SERVER_LSH PPC_BITLSHIFT(23) -#define IODA2_LXIVT_PRIORITY_MASK PPC_BITMASK(24,31) -#define IODA2_LXIVT_PRIORITY_LSH PPC_BITLSHIFT(31) -#define IODA2_LXIVT_NODE_ID_MASK PPC_BITMASK(56,63) -#define IODA2_LXIVT_NODE_ID_LSH PPC_BITLSHIFT(63) +#define IODA2_LXIVT_SERVER PPC_BITMASK(8,23) +#define IODA2_LXIVT_PRIORITY PPC_BITMASK(24,31) +#define IODA2_LXIVT_NODE_ID PPC_BITMASK(56,63) /* IVT */ -#define IODA2_IVT_SERVER_MASK PPC_BITMASK(0,23) -#define IODA2_IVT_SERVER_LSH PPC_BITLSHIFT(23) -#define IODA2_IVT_PRIORITY_MASK PPC_BITMASK(24,31) -#define IODA2_IVT_PRIORITY_LSH PPC_BITLSHIFT(31) -#define IODA2_IVT_P_MASK PPC_BITMASK(39,39) -#define IODA2_IVT_P_LSH PPC_BITLSHIFT(39) -#define IODA2_IVT_Q_MASK PPC_BITMASK(47,47) -#define IODA2_IVT_Q_LSH PPC_BITLSHIFT(47) -#define IODA2_IVT_PE_MASK PPC_BITMASK(48,63) -#define IODA2_IVT_PE_LSH PPC_BITLSHIFT(63) +#define IODA2_IVT_SERVER PPC_BITMASK(0,23) +#define IODA2_IVT_PRIORITY PPC_BITMASK(24,31) +#define IODA2_IVT_P PPC_BITMASK(39,39) +#define IODA2_IVT_Q PPC_BITMASK(47,47) +#define IODA2_IVT_PE PPC_BITMASK(48,63) /* TVT */ -#define IODA2_TVT_TABLE_ADDR_MASK PPC_BITMASK(0,47) -#define IODA2_TVT_TABLE_ADDR_LSH PPC_BITLSHIFT(47) -#define IODA2_TVT_NUM_LEVELS_MASK PPC_BITMASK(48,50) -#define IODA2_TVT_NUM_LEVELS_LSH PPC_BITLSHIFT(50) +#define IODA2_TVT_TABLE_ADDR PPC_BITMASK(0,47) +#define IODA2_TVT_NUM_LEVELS PPC_BITMASK(48,50) #define IODA2_TVE_1_LEVEL 0 #define IODA2_TVE_2_LEVELS 1 #define IODA2_TVE_3_LEVELS 2 #define IODA2_TVE_4_LEVELS 3 #define IODA2_TVE_5_LEVELS 4 -#define IODA2_TVT_TCE_TABLE_SIZE_MASK PPC_BITMASK(51,55) -#define IODA2_TVT_TCE_TABLE_SIZE_LSH PPC_BITLSHIFT(55) -#define IODA2_TVT_IO_PSIZE_MASK PPC_BITMASK(59,63) -#define IODA2_TVT_IO_PSIZE_LSH PPC_BITLSHIFT(63) +#define IODA2_TVT_TCE_TABLE_SIZE PPC_BITMASK(51,55) +#define IODA2_TVT_IO_PSIZE PPC_BITMASK(59,63) /* PESTA */ #define IODA2_PESTA_MMIO_FROZEN PPC_BIT(0) @@ -381,24 +341,17 @@ #define IODA2_PESTB_DMA_STOPPED PPC_BIT(0) /* M32DT */ -#define IODA2_M32DT_PE_MASK PPC_BITMASK(8,15) -#define IODA2_M32DT_PE_LSH PPC_BITLSHIFT(15) +#define IODA2_M32DT_PE PPC_BITMASK(8,15) /* M64BT */ #define IODA2_M64BT_ENABLE PPC_BIT(0) #define IODA2_M64BT_SINGLE_PE PPC_BIT(1) -#define IODA2_M64BT_BASE_MASK PPC_BITMASK(2,31) -#define IODA2_M64BT_BASE_LSH PPC_BITLSHIFT(31) -#define IODA2_M64BT_MASK_MASK PPC_BITMASK(34,63) -#define IODA2_M64BT_MASK_LSH PPC_BITLSHIFT(63) -#define IODA2_M64BT_SINGLE_BASE_MASK PPC_BITMASK(2,26) -#define IODA2_M64BT_SINGLE_BASE_LSH PPC_BITLSHIFT(26) -#define IODA2_M64BT_PE_HI_MASK PPC_BITMASK(27,31) -#define IODA2_M64BT_PE_HI_LSH PPC_BITLSHIFT(31) -#define IODA2_M64BT_SINGLE_MASK_MASK PPC_BITMASK(34,58) -#define IODA2_M64BT_SINGLE_MASK_LSH PPC_BITLSHIFT(58) -#define IODA2_M64BT_PE_LOW_MASK PPC_BITMASK(59,63) -#define IODA2_M64BT_PE_LOW_LSH PPC_BITLSHIFT(63) +#define IODA2_M64BT_BASE PPC_BITMASK(2,31) +#define IODA2_M64BT_MASK PPC_BITMASK(34,63) +#define IODA2_M64BT_SINGLE_BASE PPC_BITMASK(2,26) +#define IODA2_M64BT_PE_HI PPC_BITMASK(27,31) +#define IODA2_M64BT_SINGLE_MASK PPC_BITMASK(34,58) +#define IODA2_M64BT_PE_LOW PPC_BITMASK(59,63) /* * IODA2 in-memory tables @@ -412,8 +365,7 @@ #define IODA2_PEST0_MMIO_CAUSE PPC_BIT(2) #define IODA2_PEST0_CFG_READ PPC_BIT(3) #define IODA2_PEST0_CFG_WRITE PPC_BIT(4) -#define IODA2_PEST0_TTYPE_MASK PPC_BITMASK(5,7) -#define IODA2_PEST0_TTYPE_LSH PPC_BITLSHIFT(7) +#define IODA2_PEST0_TTYPE PPC_BITMASK(5,7) #define PEST_TTYPE_DMA_WRITE 0 #define PEST_TTYPE_MSI 1 #define PEST_TTYPE_DMA_READ 2 @@ -435,15 +387,11 @@ #define IODA2_PEST0_TCE_ACCESS_FAULT PPC_BIT(19) #define IODA2_PEST0_DMA_RESP_TIMEOUT PPC_BIT(20) #define IODA2_PEST0_AIB_SIZE_INVALID PPC_BIT(21) -#define IODA2_PEST0_LEM_BIT_MASK PPC_BITMASK(26,31) -#define IODA2_PEST0_LEM_BIT_LSH PPC_BITLSHIFT(31) -#define IODA2_PEST0_RID_MASK PPC_BITMASK(32,47) -#define IODA2_PEST0_RID_LSH PPC_BITLSHIFT(47) -#define IODA2_PEST0_MSI_DATA_MASK PPC_BITMASK(48,63) -#define IODA2_PEST0_MSI_DATA_LSH PPC_BITLSHIFT(63) +#define IODA2_PEST0_LEM_BIT PPC_BITMASK(26,31) +#define IODA2_PEST0_RID PPC_BITMASK(32,47) +#define IODA2_PEST0_MSI_DATA PPC_BITMASK(48,63) -#define IODA2_PEST1_FAIL_ADDR_MASK PPC_BITMASK(3,63) -#define IODA2_PEST1_FAIL_ADDR_LSH PPC_BITLSHIFT(63) +#define IODA2_PEST1_FAIL_ADDR PPC_BITMASK(3,63) #endif /* __PHB3_REGS_H */ diff --git a/include/processor.h b/include/processor.h index c15e17e..31ed72d 100644 --- a/include/processor.h +++ b/include/processor.h @@ -95,13 +95,10 @@ /* Bits in TFMR - control bits */ -#define SPR_TFMR_MAX_CYC_BET_STEPS_MASK PPC_BITMASK(0,7) -#define SPR_TFMR_MAX_CYC_BET_STEPS_LSH PPC_BITLSHIFT(7) -#define SPR_TFMR_N_CLKS_PER_STEP_MASK PPC_BITMASK(8,9) -#define SPR_TFMR_N_CLKS_PER_STEP_LSH PPC_BITLSHIFT(9) +#define SPR_TFMR_MAX_CYC_BET_STEPS PPC_BITMASK(0,7) +#define SPR_TFMR_N_CLKS_PER_STEP PPC_BITMASK(8,9) #define SPR_TFMR_MASK_HMI PPC_BIT(10) -#define SPR_TFMR_SYNC_BIT_SEL_MASK PPC_BITMASK(11,13) -#define SPR_TFMR_SYNC_BIT_SEL_LSH PPC_BITLSHIFT(13) +#define SPR_TFMR_SYNC_BIT_SEL PPC_BITMASK(11,13) #define SPR_TFMR_TB_ECLIPZ PPC_BIT(14) #define SPR_TFMR_LOAD_TOD_MOD PPC_BIT(16) #define SPR_TFMR_MOVE_CHIP_TOD_TO_TB PPC_BIT(18) @@ -109,10 +106,8 @@ /* Bits in TFMR - thread indep. status bits */ #define SPR_TFMR_HDEC_PARITY_ERROR PPC_BIT(26) #define SPR_TFMR_TBST_CORRUPT PPC_BIT(27) -#define SPR_TFMR_TBST_ENCODED_MASK PPC_BITMASK(28,31) -#define SPR_TFMR_TBST_ENCODED_LSH PPC_BITLSHIFT(31) -#define SPR_TFMR_TBST_LAST_MASK PPC_BITMASK(32,35) -#define SPR_TFMR_TBST_LAST_LSH PPC_BITLSHIFT(35) +#define SPR_TFMR_TBST_ENCODED PPC_BITMASK(28,31) +#define SPR_TFMR_TBST_LAST PPC_BITMASK(32,35) #define SPR_TFMR_TB_ENABLED PPC_BIT(40) #define SPR_TFMR_TB_VALID PPC_BIT(41) #define SPR_TFMR_TB_SYNC_OCCURED PPC_BIT(42) @@ -120,8 +115,7 @@ #define SPR_TFMR_TB_MISSING_STEP PPC_BIT(44) #define SPR_TFMR_TB_RESIDUE_ERR PPC_BIT(45) #define SPR_TFMR_FW_CONTROL_ERR PPC_BIT(46) -#define SPR_TFMR_CHIP_TOD_STATUS_MASK PPC_BITMASK(47,50) -#define SPR_TFMR_CHIP_TOD_STATUS_LSH PPC_BITLSHIFT(50) +#define SPR_TFMR_CHIP_TOD_STATUS PPC_BITMASK(47,50) #define SPR_TFMR_CHIP_TOD_INTERRUPT PPC_BIT(51) #define SPR_TFMR_CHIP_TOD_TIMEOUT PPC_BIT(54) #define SPR_TFMR_CHIP_TOD_PARITY_ERR PPC_BIT(56) @@ -147,8 +141,7 @@ #define SPR_HMER_SCOM_FIR_HMI PPC_BIT(16) #define SPR_HMER_TRIG_FIR_HMI PPC_BIT(17) #define SPR_HMER_HYP_RESOURCE_ERR PPC_BIT(20) -#define SPR_HMER_XSCOM_STATUS_MASK PPC_BITMASK(21,23) -#define SPR_HMER_XSCOM_STATUS_LSH PPC_BITLSHIFT(23) +#define SPR_HMER_XSCOM_STATUS PPC_BITMASK(21,23) /* * HMEER: initial bits for HMI interrupt enable mask. @@ -167,12 +160,9 @@ #define SPR_HID0_ENABLE_ATTN PPC_BIT(31) /* PVR bits */ -#define SPR_PVR_TYPE_MASK 0xffff0000 -#define SPR_PVR_TYPE_LSH 16 -#define SPR_PVR_VERS_MAJ_MASK 0x00000f00 -#define SPR_PVR_VERS_MAJ_LSH 8 -#define SPR_PVR_VERS_MIN_MASK 0x000000ff -#define SPR_PVR_VERS_MIN_LSH 0 +#define SPR_PVR_TYPE 0xffff0000 +#define SPR_PVR_VERS_MAJ 0x00000f00 +#define SPR_PVR_VERS_MIN 0x000000ff #define PVR_TYPE(_pvr) GETFIELD(SPR_PVR_TYPE, _pvr) #define PVR_VERS_MAJ(_pvr) GETFIELD(SPR_PVR_VERS_MAJ, _pvr) diff --git a/include/psi.h b/include/psi.h index 85057f5..7e7a24c 100644 --- a/include/psi.h +++ b/include/psi.h @@ -92,14 +92,12 @@ #define PSIHB_XIVR_LOCAL_ERR 0x78 #define PSIHB_XIVR_HOST_ERR 0x80 #define PSIHB_ISRN 0x88 -#define PSIHB_ISRN_COMP_MASK PPC_BITMASK(0,18) -#define PSIHB_ISRN_COMP_LSH PPC_BITLSHIFT(18) +#define PSIHB_ISRN_COMP PPC_BITMASK(0,18) #define PSIHB_ISRN_IRQ_MUX PPC_BIT(28) #define PSIHB_ISRN_IRQ_RESET PPC_BIT(29) #define PSIHB_ISRN_DOWNSTREAM_EN PPC_BIT(30) #define PSIHB_ISRN_UPSTREAM_EN PPC_BIT(31) -#define PSIHB_ISRN_MASK_MASK PPC_BITMASK(32,50) -#define PSIHB_ISRN_MASK_LSH PPC_BITLSHIFT(50) +#define PSIHB_ISRN_MASK PPC_BITMASK(32,50) #define PSIHB_IRQ_STATUS 0x58 #define PSIHB_IRQ_STAT_OCC PPC_BIT(27) |