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-rw-r--r--hw/npu.c20
-rw-r--r--include/npu-regs.h4
2 files changed, 16 insertions, 8 deletions
diff --git a/hw/npu.c b/hw/npu.c
index bca53df..11e8b97 100644
--- a/hw/npu.c
+++ b/hw/npu.c
@@ -1614,14 +1614,20 @@ static void npu_create_devices(struct dt_node *dn, struct npu *p)
struct npu_dev *dev;
struct dt_node *npu_dn, *link;
uint32_t npu_phandle, index = 0;
- uint64_t buid;
+ uint64_t buid_reg;
uint64_t lsisrcid;
+ uint64_t buid;
+
+
+ /* The bits in the LSI ID Base register are always compared and
+ * can be set to 0 in the buid base and mask fields. The
+ * buid (bus unit id) is the full irq minus the last 4 bits. */
+ lsisrcid = GETFIELD(NPU_LSI_SRC_ID_BASE, NPU_LSI_SRC_ID_BASE);
+ buid = p8_chip_irq_block_base(p->chip_id, P8_IRQ_BLOCK_MISC) >> 4;
- lsisrcid = GETFIELD(NPU_LSI_SRC_ID_BASE,
- in_be64(p->at_regs + NPU_LSI_SOURCE_ID));
- buid = SETFIELD(NP_BUID_BASE, 0ull,
- (p8_chip_irq_block_base(p->chip_id, P8_IRQ_BLOCK_MISC) | lsisrcid));
- buid |= NP_BUID_ENABLE;
+ buid_reg = SETFIELD(NP_IRQ_LEVELS, NP_BUID_ENABLE, ~0);
+ buid_reg = SETFIELD(NP_BUID_MASK, buid_reg, ~lsisrcid);
+ buid_reg = SETFIELD(NP_BUID_BASE, buid_reg, (buid & ~lsisrcid));
/* Get the npu node which has the links which we expand here
* into pci like devices attached to our emulated phb. */
@@ -1661,7 +1667,7 @@ static void npu_create_devices(struct dt_node *dn, struct npu *p)
dev->lane_mask = dt_prop_get_u32(link, "ibm,npu-lane-mask");
/* Setup BUID/ISRN */
- xscom_write(p->chip_id, dev->xscom + NX_NP_BUID, buid);
+ xscom_write(p->chip_id, dev->xscom + NX_NP_BUID, buid_reg);
/* Setup emulated config space */
for (j = 0; j < NPU_DEV_CFG_MAX; j++)
diff --git a/include/npu-regs.h b/include/npu-regs.h
index f663a98..4f1a19c 100644
--- a/include/npu-regs.h
+++ b/include/npu-regs.h
@@ -52,7 +52,9 @@
#define NX_AS_CMD_CFG 0x12
#define NX_NP_BUID 0x13
#define NP_BUID_ENABLE PPC_BIT(0)
-#define NP_BUID_BASE PPC_BITMASK(1,23)
+#define NP_BUID_BASE PPC_BITMASK(1,15)
+#define NP_IRQ_LEVELS PPC_BITMASK(16,23)
+#define NP_BUID_MASK PPC_BITMASK(24,32)
#define NX_TL_CMD_CR 0x20
#define NX_TL_CMD_D_CR 0x21
#define NX_TL_RSP_CR 0x22