diff options
| -rw-r--r-- | core/direct-controls.c | 26 | ||||
| -rw-r--r-- | core/hmi.c | 26 | ||||
| -rw-r--r-- | hw/occ.c | 1 | ||||
| -rw-r--r-- | hw/slw.c | 2 | ||||
| -rw-r--r-- | hw/xscom.c | 5 | ||||
| -rw-r--r-- | include/xscom-p8-regs.h | 62 | ||||
| -rw-r--r-- | include/xscom-p9-regs.h | 46 | ||||
| -rw-r--r-- | include/xscom.h | 5 |
8 files changed, 119 insertions, 54 deletions
diff --git a/core/direct-controls.c b/core/direct-controls.c index 1d0f681..28191b7 100644 --- a/core/direct-controls.c +++ b/core/direct-controls.c @@ -19,6 +19,8 @@ #include <opal.h> #include <cpu.h> #include <xscom.h> +#include <xscom-p8-regs.h> +#include <xscom-p9-regs.h> #include <timebase.h> #include <chip.h> @@ -55,11 +57,6 @@ static void mambo_stop_cpu(struct cpu_thread *cpu) /**************** POWER8 direct controls ****************/ -#define P8_EX_TCTL_DIRECT_CONTROLS(t) (0x10013000 + (t) * 0x10) -#define P8_DIRECT_CTL_STOP PPC_BIT(63) -#define P8_DIRECT_CTL_PRENAP PPC_BIT(47) -#define P8_DIRECT_CTL_SRESET PPC_BIT(60) - static int p8_core_set_special_wakeup(struct cpu_thread *cpu) { uint64_t val, poll_target, stamp; @@ -267,29 +264,10 @@ static int p8_sreset_thread(struct cpu_thread *cpu) /**************** POWER9 direct controls ****************/ -#define P9_RAS_STATUS 0x10a02 -#define P9_THREAD_QUIESCED(t) PPC_BITMASK(0 + 8*(t), 3 + 8*(t)) /* Long running instructions may take time to complete. Timeout 100ms */ #define P9_QUIESCE_POLL_INTERVAL 100 #define P9_QUIESCE_TIMEOUT 100000 -#define P9_CORE_THREAD_STATE 0x10ab3 -#define P9_THREAD_INFO 0x10a9b - -#define P9_EC_DIRECT_CONTROLS 0x10a9c -#define P9_THREAD_STOP(t) PPC_BIT(7 + 8*(t)) -#define P9_THREAD_CONT(t) PPC_BIT(6 + 8*(t)) -#define P9_THREAD_SRESET(t) PPC_BIT(4 + 8*(t)) -#define P9_THREAD_CLEAR_MAINT(t) PPC_BIT(3 + 8*(t)) -#define P9_THREAD_PWR(t) PPC_BIT(32 + 8*(t)) - -/* EC_PPM_SPECIAL_WKUP_HYP */ -#define P9_SPWKUP_SET PPC_BIT(0) - -#define P9_EC_PPM_SSHHYP 0x0114 -#define P9_CORE_GATED PPC_BIT(0) -#define P9_SPECIAL_WKUP_DONE PPC_BIT(1) - /* Waking may take up to 5ms for deepest sleep states. Set timeout to 100ms */ #define P9_SPWKUP_POLL_INTERVAL 100 #define P9_SPWKUP_TIMEOUT 100000 @@ -22,6 +22,7 @@ #include <processor.h> #include <chiptod.h> #include <xscom.h> +#include <xscom-p8-regs.h> #include <xscom-p9-regs.h> #include <pci.h> #include <cpu.h> @@ -162,31 +163,6 @@ ((((1UL) << (t_count)) - 1) << ((s_id) * (t_count))) #define SINGLE_THREAD_MASK(t_id) ((1UL) << (t_id)) -/* xscom addresses for core FIR (Fault Isolation Register) */ -#define P8_CORE_FIR 0x10013100 -#define P9_CORE_FIR 0x20010A40 - -/* And core WOF (Whose On First) */ -#define P9_CORE_WOF 0x20010A48 - -/* xscom addresses for pMisc Receive Malfunction Alert Register */ -#define P8_MALFUNC_ALERT 0x02020011 -#define P9_MALFUNC_ALERT 0x00090022 - -#define P8_NX_STATUS_REG 0x02013040 /* NX status register */ -#define P8_NX_DMA_ENGINE_FIR 0x02013100 /* DMA & Engine FIR Data Register */ -#define P8_NX_PBI_FIR 0x02013080 /* PowerBus Interface FIR Register */ - -#define P9_NX_STATUS_REG 0x02011040 /* NX status register */ -#define P9_NX_DMA_ENGINE_FIR 0x02011100 /* DMA & Engine FIR Data Register */ -#define P9_NX_PBI_FIR 0x02011080 /* PowerBus Interface FIR Register */ - -/* - * Bit 54 from NX status register is set to 1 when HMI interrupt is triggered - * due to NX checksop. - */ -#define NX_HMI_ACTIVE PPC_BIT(54) - /* * Number of iterations for the various timeouts. We can't use the timebase * as it might be broken. We measured experimentally that 40 millions loops @@ -16,6 +16,7 @@ #include <skiboot.h> #include <xscom.h> +#include <xscom-p8-regs.h> #include <io.h> #include <cpu.h> #include <chip.h> @@ -19,6 +19,8 @@ */ #include <skiboot.h> #include <xscom.h> +#include <xscom-p8-regs.h> +#include <xscom-p9-regs.h> #include <io.h> #include <cpu.h> #include <chip.h> @@ -164,6 +164,11 @@ static int xscom_clear_error(uint32_t gcid, uint32_t pcb_addr) if (proc_gen != proc_gen_p9) return 0; +/* xscom clear address range/mask */ +#define XSCOM_CLEAR_RANGE_START 0x20010A00 +#define XSCOM_CLEAR_RANGE_END 0x20010ABF +#define XSCOM_CLEAR_RANGE_MASK 0x200FFBFF + /* * Due to a hardware issue where core responding to scom was delayed * due to thread reconfiguration, leaves the scom logic in a state diff --git a/include/xscom-p8-regs.h b/include/xscom-p8-regs.h new file mode 100644 index 0000000..3523272 --- /dev/null +++ b/include/xscom-p8-regs.h @@ -0,0 +1,62 @@ +#ifndef __XSCOM_P8_REGS_H__ +#define __XSCOM_P8_REGS_H__ + +/* Core FIR (Fault Isolation Register) */ +#define P8_CORE_FIR 0x10013100 + +/* Direct controls */ +#define P8_EX_TCTL_DIRECT_CONTROLS(t) (0x10013000 + (t) * 0x10) +#define P8_DIRECT_CTL_STOP PPC_BIT(63) +#define P8_DIRECT_CTL_PRENAP PPC_BIT(47) +#define P8_DIRECT_CTL_SRESET PPC_BIT(60) + +/* pMisc Receive Malfunction Alert Register */ +#define P8_MALFUNC_ALERT 0x02020011 + +#define P8_NX_STATUS_REG 0x02013040 /* NX status register */ +#define P8_NX_DMA_ENGINE_FIR 0x02013100 /* DMA & Engine FIR Data Register */ +#define P8_NX_PBI_FIR 0x02013080 /* PowerBus Interface FIR Register */ + +/* + * Bit 54 from NX status register is set to 1 when HMI interrupt is triggered + * due to NX checksop. + */ +#define NX_HMI_ACTIVE PPC_BIT(54) + +/* Per core power mgt registers */ +#define PM_OHA_MODE_REG 0x1002000D +#define L2_FIR_ACTION1 0x10012807 + +/* EX slave per-core power mgt slave regisers */ +#define EX_PM_GP0 0x0100 +#define EX_PM_GP1 0x0103 +#define EX_PM_CLEAR_GP1 0x0104 /* AND SCOM */ +#define EX_PM_SET_GP1 0x0105 /* OR SCOM */ +#define EX_PM_SPECIAL_WAKEUP_FSP 0x010B +#define EX_PM_SPECIAL_WAKEUP_OCC 0x010C +#define EX_PM_SPECIAL_WAKEUP_PHYP 0x010D +#define EX_PM_IDLE_STATE_HISTORY_PHYP 0x0110 +#define EX_PM_IDLE_STATE_HISTORY_FSP 0x0111 +#define EX_PM_IDLE_STATE_HISTORY_OCC 0x0112 +#define EX_PM_IDLE_STATE_HISTORY_PERF 0x0113 +#define EX_PM_CORE_PFET_VRET 0x0130 +#define EX_PM_CORE_ECO_VRET 0x0150 +#define EX_PM_PPMSR 0x0153 +#define EX_PM_PPMCR 0x0159 + +/* Power mgt bits in GP0 */ +#define EX_PM_GP0_SPECIAL_WAKEUP_DONE PPC_BIT(31) + +/* Power mgt settings in GP1 */ +#define EX_PM_SETUP_GP1_FAST_SLEEP 0xD800000000000000ULL +#define EX_PM_SETUP_GP1_DEEP_SLEEP 0x2400000000000000ULL +#define EX_PM_SETUP_GP1_FAST_SLEEP_DEEP_WINKLE 0xC400000000000000ULL +#define EX_PM_GP1_SLEEP_WINKLE_MASK 0xFC00000000000000ULL +#define EX_PM_SETUP_GP1_PM_SPR_OVERRIDE_EN 0x0010000000000000ULL +#define EX_PM_SETUP_GP1_DPLL_FREQ_OVERRIDE_EN 0x0020000000000000ULL + +/* Fields in history regs */ +#define EX_PM_IDLE_ST_HIST_PM_STATE_MASK PPC_BITMASK(0, 2) +#define EX_PM_IDLE_ST_HIST_PM_STATE_LSH PPC_BITLSHIFT(2) + +#endif /* __XSCOM_P8_REGS_H__ */ diff --git a/include/xscom-p9-regs.h b/include/xscom-p9-regs.h index 42dd426..2c9dc6b 100644 --- a/include/xscom-p9-regs.h +++ b/include/xscom-p9-regs.h @@ -1,6 +1,46 @@ #ifndef __XSCOM_P9_REGS_H__ #define __XSCOM_P9_REGS_H__ +/* Core FIR (Fault Isolation Register) */ +#define P9_CORE_FIR 0x20010A40 + +/* Core WOF (Whose On First) */ +#define P9_CORE_WOF 0x20010A48 + +/* pMisc Receive Malfunction Alert Register */ +#define P9_MALFUNC_ALERT 0x00090022 + +#define P9_NX_STATUS_REG 0x02011040 /* NX status register */ +#define P9_NX_DMA_ENGINE_FIR 0x02011100 /* DMA & Engine FIR Data Register */ +#define P9_NX_PBI_FIR 0x02011080 /* PowerBus Interface FIR Register */ + +/* + * Bit 54 from NX status register is set to 1 when HMI interrupt is triggered + * due to NX checksop. + */ +#define NX_HMI_ACTIVE PPC_BIT(54) + +/* Direct controls */ +#define P9_EC_DIRECT_CONTROLS 0x10a9c +#define P9_THREAD_STOP(t) PPC_BIT(7 + 8*(t)) +#define P9_THREAD_CONT(t) PPC_BIT(6 + 8*(t)) +#define P9_THREAD_SRESET(t) PPC_BIT(4 + 8*(t)) +#define P9_THREAD_CLEAR_MAINT(t) PPC_BIT(3 + 8*(t)) +#define P9_THREAD_PWR(t) PPC_BIT(32 + 8*(t)) + +#define P9_RAS_STATUS 0x10a02 +#define P9_THREAD_QUIESCED(t) PPC_BITMASK(0 + 8*(t), 3 + 8*(t)) + +#define P9_CORE_THREAD_STATE 0x10ab3 +#define P9_THREAD_INFO 0x10a9b + +/* EC_PPM_SPECIAL_WKUP_HYP */ +#define P9_SPWKUP_SET PPC_BIT(0) + +#define P9_EC_PPM_SSHHYP 0x0114 +#define P9_CORE_GATED PPC_BIT(0) +#define P9_SPECIAL_WKUP_DONE PPC_BIT(1) + /* EX (core pair) registers, use XSCOM_ADDR_P9_EX to access */ #define P9X_EX_NCU_STATUS_REG 0x1100f #define P9X_EX_NCU_SPEC_BAR 0x11010 @@ -33,4 +73,10 @@ #define PB_CFG_CHG_RATE_GP_MASTER PPC_BIT(2) #define PB_CFG_PUMP_MODE PPC_BIT(54) +/* Power 9 EC slave per-core power mgt slave registers */ +#define EC_PPM_SPECIAL_WKUP_OTR 0x010A +#define EC_PPM_SPECIAL_WKUP_FSP 0x010B +#define EC_PPM_SPECIAL_WKUP_OCC 0x010C +#define EC_PPM_SPECIAL_WKUP_HYP 0x010D + #endif /* __XSCOM_P9_REGS_H__ */ diff --git a/include/xscom.h b/include/xscom.h index 9853224..649de67 100644 --- a/include/xscom.h +++ b/include/xscom.h @@ -209,11 +209,6 @@ /* Max number of retries for xscom clearing recovery. */ #define XSCOM_CLEAR_MAX_RETRIES 10 -/* xscom clear address range/mask */ -#define XSCOM_CLEAR_RANGE_START 0x20010A00 -#define XSCOM_CLEAR_RANGE_END 0x20010ABF -#define XSCOM_CLEAR_RANGE_MASK 0x200FFBFF - /* Retry count after which to reset XSCOM, if still busy */ #define XSCOM_BUSY_RESET_THRESHOLD 1000 |