diff options
| -rw-r--r-- | hw/npu2-common.c | 1 | ||||
| -rw-r--r-- | hw/npu2-opencapi.c | 2 | ||||
| -rw-r--r-- | hw/npu2.c | 2 | ||||
| -rw-r--r-- | include/npu2.h | 20 |
4 files changed, 22 insertions, 3 deletions
diff --git a/hw/npu2-common.c b/hw/npu2-common.c index 51ecd0c..4e5b104 100644 --- a/hw/npu2-common.c +++ b/hw/npu2-common.c @@ -537,7 +537,6 @@ static struct npu2 *setup_npu(struct dt_node *dn) npu->index = dt_prop_get_u32(dn, "ibm,npu-index"); npu->chip_id = gcid; npu->xscom_base = dt_get_address(dn, 0, NULL); - npu->phb_index = dt_prop_get_u32(dn, "ibm,phb-index"); init_lock(&npu->i2c_lock); npu->i2c_pin_mode = ~0; // input mode by default diff --git a/hw/npu2-opencapi.c b/hw/npu2-opencapi.c index b8ebc83..0d371d5 100644 --- a/hw/npu2-opencapi.c +++ b/hw/npu2-opencapi.c @@ -1768,6 +1768,8 @@ static void setup_device(struct npu2_dev *dev) dt_add_property_strings(dn_phb, "device_type", "pciex"); dt_add_property(dn_phb, "reg", mm_win, sizeof(mm_win)); dt_add_property_cells(dn_phb, "ibm,npu-index", dev->npu->index); + dt_add_property_cells(dn_phb, "ibm,phb-index", + npu2_get_phb_index(dev->brick_index)); dt_add_property_cells(dn_phb, "ibm,chip-id", dev->npu->chip_id); dt_add_property_cells(dn_phb, "ibm,xscom-base", dev->npu->xscom_base); dt_add_property_cells(dn_phb, "ibm,npcq", dev->npu->dt_node->phandle); @@ -1478,7 +1478,7 @@ int npu2_nvlink_init_npu(struct npu2 *npu) "ibm,ioda2-npu2-phb"); dt_add_property_strings(np, "device_type", "pciex"); dt_add_property(np, "reg", reg, sizeof(reg)); - dt_add_property_cells(np, "ibm,phb-index", npu->phb_index); + dt_add_property_cells(np, "ibm,phb-index", npu2_get_phb_index(0)); dt_add_property_cells(np, "ibm,npu-index", npu->index); dt_add_property_cells(np, "ibm,chip-id", npu->chip_id); dt_add_property_cells(np, "ibm,xscom-base", npu->xscom_base); diff --git a/include/npu2.h b/include/npu2.h index d2a3430..309a7c7 100644 --- a/include/npu2.h +++ b/include/npu2.h @@ -178,7 +178,6 @@ struct npu2 { /* NVLink */ struct phb phb_nvlink; - uint32_t phb_index; /* OCAPI */ uint64_t i2c_port_id_ocapi; @@ -256,4 +255,23 @@ int64_t npu2_set_relaxed_order(struct phb *phb, uint32_t gcid, int pec, void npu2_opencapi_set_broken(struct npu2 *npu, int brick); +#define NPU2_PHB_INDEX_BASE 7 +/* to avoid conflicts with PCI and for historical reasons */ + +static inline int npu2_get_phb_index(unsigned int brick_index) +{ + /* + * There's one virtual PHB per brick with opencapi, so we no + * longer have a 1-to-1 mapping between a NPU and a virtual + * PHB. And we want a static phb-index, as it is needed to use + * a slot table on some platforms. So we associate a per-chip + * phb-index based on the brick index. + * + * nvlink only creates one virtual PHB per chip, so it is + * treated as if using brick 0, which is never used by + * opencapi. + */ + return NPU2_PHB_INDEX_BASE + brick_index; +} + #endif /* __NPU2_H */ |