diff options
| -rw-r--r-- | hw/npu-opal.c | 64 | ||||
| -rw-r--r-- | hw/npu2-opencapi.c | 40 | ||||
| -rw-r--r-- | include/npu2.h | 7 |
3 files changed, 76 insertions, 35 deletions
diff --git a/hw/npu-opal.c b/hw/npu-opal.c index c7f5f9f..73158b1 100644 --- a/hw/npu-opal.c +++ b/hw/npu-opal.c @@ -8,6 +8,8 @@ #include <phb4.h> #include <npu2.h> +#define TL_RATE_BUF_SIZE 32 + static int64_t opal_npu_init_context(uint64_t phb_id, int pid __unused, uint64_t msr, uint64_t bdf) { @@ -161,3 +163,65 @@ static int64_t opal_npu_get_relaxed_order(uint64_t phb_id, return phb4->ro_state; } opal_call(OPAL_NPU_GET_RELAXED_ORDER, opal_npu_get_relaxed_order, 2); + +#define MAX_PE_HANDLE ((1 << 15) - 1) + +static int64_t opal_npu_spa_setup(uint64_t phb_id, uint32_t bdfn, + uint64_t addr, uint64_t PE_mask) +{ + struct phb *phb = pci_get_phb(phb_id); + + if (!phb) + return OPAL_PARAMETER; + + /* 4k aligned */ + if (addr & 0xFFF) + return OPAL_PARAMETER; + + if (PE_mask > 15) + return OPAL_PARAMETER; + + if (phb->phb_type == phb_type_npu_v2_opencapi) + return npu2_opencapi_spa_setup(phb, bdfn, addr, PE_mask); + + return OPAL_PARAMETER; +} +opal_call(OPAL_NPU_SPA_SETUP, opal_npu_spa_setup, 4); + +static int64_t opal_npu_spa_clear_cache(uint64_t phb_id, uint32_t bdfn, + uint64_t PE_handle) +{ + struct phb *phb = pci_get_phb(phb_id); + + if (!phb) + return OPAL_PARAMETER; + + if (PE_handle > MAX_PE_HANDLE) + return OPAL_PARAMETER; + + if (phb->phb_type == phb_type_npu_v2_opencapi) + return npu2_opencapi_spa_clear_cache(phb, bdfn, PE_handle); + + return OPAL_PARAMETER; +} +opal_call(OPAL_NPU_SPA_CLEAR_CACHE, opal_npu_spa_clear_cache, 3); + +static int64_t opal_npu_tl_set(uint64_t phb_id, uint32_t bdfn, + long capabilities, uint64_t rate_phys, int rate_sz) +{ + struct phb *phb = pci_get_phb(phb_id); + char *rate = (char *) rate_phys; + + if (!phb) + return OPAL_PARAMETER; + + if (!opal_addr_valid(rate) || rate_sz != TL_RATE_BUF_SIZE) + return OPAL_PARAMETER; + + if (phb->phb_type == phb_type_npu_v2_opencapi) + return npu2_opencapi_tl_set(phb, bdfn, capabilities, + rate); + + return OPAL_PARAMETER; +} +opal_call(OPAL_NPU_TL_SET, opal_npu_tl_set, 5); diff --git a/hw/npu2-opencapi.c b/hw/npu2-opencapi.c index 035c6cd..272f924 100644 --- a/hw/npu2-opencapi.c +++ b/hw/npu2-opencapi.c @@ -41,7 +41,6 @@ #define NPU_IRQ_LEVELS_XSL 23 #define MAX_PE_HANDLE ((1 << 15) - 1) #define TL_MAX_TEMPLATE 63 -#define TL_RATE_BUF_SIZE 32 #define OCAPI_SLOT_NORMAL PCI_SLOT_STATE_NORMAL #define OCAPI_SLOT_LINK PCI_SLOT_STATE_LINK @@ -1957,24 +1956,13 @@ void npu2_opencapi_set_broken(struct npu2 *npu, int brick) } } -static int64_t opal_npu_spa_setup(uint64_t phb_id, uint32_t __unused bdfn, +int64_t npu2_opencapi_spa_setup(struct phb *phb, uint32_t __unused bdfn, uint64_t addr, uint64_t PE_mask) { uint64_t stack, block, offset, reg; - struct phb *phb = pci_get_phb(phb_id); struct npu2_dev *dev; int rc; - if (!phb || phb->phb_type != phb_type_npu_v2_opencapi) - return OPAL_PARAMETER; - - /* 4k aligned */ - if (addr & 0xFFF) - return OPAL_PARAMETER; - - if (PE_mask > 15) - return OPAL_PARAMETER; - dev = phb_to_npu2_dev_ocapi(phb); if (!dev) return OPAL_PARAMETER; @@ -1986,7 +1974,6 @@ static int64_t opal_npu_spa_setup(uint64_t phb_id, uint32_t __unused bdfn, else offset = NPU2_XSL_PSL_SPAP_A0; - lock(&dev->npu->lock); /* * set the SPAP used by the device @@ -2024,22 +2011,14 @@ out: unlock(&dev->npu->lock); return rc; } -opal_call(OPAL_NPU_SPA_SETUP, opal_npu_spa_setup, 4); -static int64_t opal_npu_spa_clear_cache(uint64_t phb_id, uint32_t __unused bdfn, - uint64_t PE_handle) +int64_t npu2_opencapi_spa_clear_cache(struct phb *phb, uint32_t __unused bdfn, + uint64_t PE_handle) { uint64_t cc_inv, stack, block, reg, rc; uint32_t retries = 5; - struct phb *phb = pci_get_phb(phb_id); struct npu2_dev *dev; - if (!phb || phb->phb_type != phb_type_npu_v2_opencapi) - return OPAL_PARAMETER; - - if (PE_handle > MAX_PE_HANDLE) - return OPAL_PARAMETER; - dev = phb_to_npu2_dev_ocapi(phb); if (!dev) return OPAL_PARAMETER; @@ -2077,7 +2056,6 @@ out: unlock(&dev->npu->lock); return rc; } -opal_call(OPAL_NPU_SPA_CLEAR_CACHE, opal_npu_spa_clear_cache, 3); static int get_template_rate(unsigned int templ, char *rate_buf) { @@ -2101,19 +2079,12 @@ static bool is_template_supported(unsigned int templ, long capabilities) return !!(capabilities & (1ull << templ)); } -static int64_t opal_npu_tl_set(uint64_t phb_id, uint32_t __unused bdfn, - long capabilities, uint64_t rate_phys, int rate_sz) +int64_t npu2_opencapi_tl_set(struct phb *phb, uint32_t __unused bdfn, + long capabilities, char *rate) { - struct phb *phb = pci_get_phb(phb_id); struct npu2_dev *dev; uint64_t stack, block, reg, templ_rate; int i, rate_pos; - char *rate = (char *) rate_phys; - - if (!phb || phb->phb_type != phb_type_npu_v2_opencapi) - return OPAL_PARAMETER; - if (!opal_addr_valid(rate) || rate_sz != TL_RATE_BUF_SIZE) - return OPAL_PARAMETER; dev = phb_to_npu2_dev_ocapi(phb); if (!dev) @@ -2157,7 +2128,6 @@ static int64_t opal_npu_tl_set(uint64_t phb_id, uint32_t __unused bdfn, OCAPIDBG(dev, "OTL configuration 1 register set to %llx\n", reg); return OPAL_SUCCESS; } -opal_call(OPAL_NPU_TL_SET, opal_npu_tl_set, 5); static void set_mem_bar(struct npu2_dev *dev, uint64_t base, uint64_t size) { diff --git a/include/npu2.h b/include/npu2.h index eb7c455..23b06b4 100644 --- a/include/npu2.h +++ b/include/npu2.h @@ -271,4 +271,11 @@ static inline int npu2_get_phb_index(unsigned int brick_index) return NPU2_PHB_INDEX_BASE + brick_index; } +int64_t npu2_opencapi_spa_setup(struct phb *phb, uint32_t __unused bdfn, + uint64_t addr, uint64_t PE_mask); +int64_t npu2_opencapi_spa_clear_cache(struct phb *phb, uint32_t __unused bdfn, + uint64_t PE_handle); +int64_t npu2_opencapi_tl_set(struct phb *phb, uint32_t __unused bdfn, + long capabilities, char *rate); + #endif /* __NPU2_H */ |