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-rw-r--r--hw/xive.c16
-rw-r--r--include/xive.h4
2 files changed, 16 insertions, 4 deletions
diff --git a/hw/xive.c b/hw/xive.c
index a088099..705d82a 100644
--- a/hw/xive.c
+++ b/hw/xive.c
@@ -3357,13 +3357,21 @@ static int64_t opal_xive_set_queue_info(uint64_t vp, uint32_t prio,
if (qflags & OPAL_XIVE_EQ_ALWAYS_NOTIFY)
eq.w0 |= EQ_W0_UCOND_NOTIFY;
- /* Check enable transitionn */
+ /* Escalation flag */
+ if (qflags & OPAL_XIVE_EQ_ESCALATE)
+ eq.w0 |= EQ_W0_ESCALATE_CTL;
+
+ /* Check enable transition. On any transition we clear PQ,
+ * set the generation bit, clear the offset and mask the
+ * escalation interrupt
+ */
if ((qflags & OPAL_XIVE_EQ_ENABLED) && !(eq.w0 & EQ_W0_VALID)) {
- /* Clear PQ bits, set G, clear offset */
- eq.w1 = EQ_W1_GENERATION;
eq.w0 |= EQ_W0_VALID;
- } else if (!(qflags & OPAL_XIVE_EQ_ENABLED))
+ eq.w1 = EQ_W1_GENERATION | EQ_W1_ESe_Q;
+ } else if (!(qflags & OPAL_XIVE_EQ_ENABLED)) {
eq.w0 &= ~EQ_W0_VALID;
+ eq.w1 = EQ_W1_GENERATION | EQ_W1_ESe_Q;
+ }
/* Update EQ, non-synchronous */
lock(&x->lock);
diff --git a/include/xive.h b/include/xive.h
index c7b96fa..6f2bad3 100644
--- a/include/xive.h
+++ b/include/xive.h
@@ -364,7 +364,11 @@ struct xive_eq {
#define EQ_W0_HWDEP PPC_BITMASK32(24,31)
uint32_t w1;
#define EQ_W1_ESn PPC_BITMASK32(0,1)
+#define EQ_W1_ESn_P PPC_BIT32(0)
+#define EQ_W1_ESn_Q PPC_BIT32(1)
#define EQ_W1_ESe PPC_BITMASK32(2,3)
+#define EQ_W1_ESe_P PPC_BIT32(2)
+#define EQ_W1_ESe_Q PPC_BIT32(3)
#define EQ_W1_GENERATION PPC_BIT32(9)
#define EQ_W1_PAGE_OFF PPC_BITMASK32(10,31)
uint32_t w2;