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| author | Prem Shanker Jha <premjha2@in.ibm.com> | 2017-11-10 07:55:37 -0600 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2018-01-24 17:19:56 +1100 |
| commit | 08188269016392f2d42835ef4b8548c0f312f941 (patch) | |
| tree | 8630a8d1da6caa92cf3958cde7588732a4b9a8ec /libpore | |
| parent | 28b94285ba3a8c905c00f8b2c73e150bb88399c0 (diff) | |
| download | skiboot-08188269016392f2d42835ef4b8548c0f312f941.zip skiboot-08188269016392f2d42835ef4b8548c0f312f941.tar.gz skiboot-08188269016392f2d42835ef4b8548c0f312f941.tar.bz2 | |
PM: Fixed generation of MTSPR instruction in STOP API.
STOP API generates SPR restore instruction for a given SPR.
Commit fixes the generation of mtspr instruction by API.
Problem will show up only when API is changed to generate
restore instruction using a GPR other than R0.
CQ: SW407799
Change-Id: I2a841a9aae417b7bcd92a323197d9c6a1f3cb149
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49525
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: STEWART E. SMITH <stewart@linux.vnet.ibm.com>
Dev-Ready: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49529
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'libpore')
| -rw-r--r-- | libpore/p9_stop_api.C | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/libpore/p9_stop_api.C b/libpore/p9_stop_api.C index 7242c42..5c0f2e5 100644 --- a/libpore/p9_stop_api.C +++ b/libpore/p9_stop_api.C @@ -258,7 +258,7 @@ static uint32_t getMtsprInstruction( const uint16_t i_Rs, const uint16_t i_Spr ) uint32_t mtsprInstOpcode = 0; uint32_t temp = (( i_Spr & 0x03FF ) << 11); mtsprInstOpcode = (uint8_t)i_Rs << 21; - mtsprInstOpcode = ( temp & 0x0000F800 ) << 5; + mtsprInstOpcode |= ( temp & 0x0000F800 ) << 5; mtsprInstOpcode |= ( temp & 0x001F0000 ) >> 5; mtsprInstOpcode |= MTSPR_BASE_OPCODE; |