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| author | Cédric Le Goater <clg@kaod.org> | 2021-08-04 12:51:23 +0530 |
|---|---|---|
| committer | Vasant Hegde <hegdevasant@linux.vnet.ibm.com> | 2021-08-06 12:29:09 +0530 |
| commit | fd422c41941de527c019c30b779d826fdf43b036 (patch) | |
| tree | c125b4dab0d9af82cdb083097517209ac35704be /include | |
| parent | e59cbfa720845c09b7b601e03dd75b73ab4baf8d (diff) | |
| download | skiboot-fd422c41941de527c019c30b779d826fdf43b036.zip skiboot-fd422c41941de527c019c30b779d826fdf43b036.tar.gz skiboot-fd422c41941de527c019c30b779d826fdf43b036.tar.bz2 | |
xive/p10: Activate has_array when PQ_disable is available
hash_array is an Internal cache hashing optimization. It tracks for
ESBs where the original trigger came from so that we avoid getting the
EAS into the cache twice.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/xive2-regs.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/xive2-regs.h b/include/xive2-regs.h index 4638c3d..c2ed265 100644 --- a/include/xive2-regs.h +++ b/include/xive2-regs.h @@ -230,6 +230,8 @@ /* ESBC configuration */ #define X_VC_ESBC_CFG 0x148 #define VC_ESBC_CFG 0x240 +#define VC_ESBC_CFG_HASH_ARRAY_ENABLE PPC_BIT(40) +#define VC_ESBC_CFG_HASH_STORE_MODE PPC_BITMASK(41,42) #define VC_ESBC_CFG_SPLIT_MODE PPC_BIT(56) /* EASC flush control register */ |