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authorNicholas Piggin <npiggin@gmail.com>2019-11-11 15:44:46 +1000
committerOliver O'Halloran <oohall@gmail.com>2019-11-11 18:35:00 +1100
commitef7c7de83586150cfc29c24e80efe6e8399c5479 (patch)
treed1b23b2b2baf8ad6bc66a849d27f4f3d4507da40 /include
parent40558797f16270d2727be0596a36a6fca56b0a44 (diff)
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psi: update registers to reflect >= P8 PHBSCR
Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Diffstat (limited to 'include')
-rw-r--r--include/psi.h8
1 files changed, 2 insertions, 6 deletions
diff --git a/include/psi.h b/include/psi.h
index 8e3f188..635d2ce 100644
--- a/include/psi.h
+++ b/include/psi.h
@@ -32,15 +32,10 @@
#define PSIHB_TAR_256K_ENTRIES 2 /* P8 only */
#define PSIHB_TAR_512K_ENTRIES 4 /* P8 only */
-/* PSI Host Bridge Control Register
- *
- * note: TCE_ENABLE moved to the new PSIHB_PHBSCR on P8 but is
- * the same bit position
- */
+/* PSI Host Bridge Control Register */
#define PSIHB_CR 0x20
#define PSIHB_CR_FSP_CMD_ENABLE PPC_BIT(0)
#define PSIHB_CR_FSP_MMIO_ENABLE PPC_BIT(1)
-#define PSIHB_CR_TCE_ENABLE PPC_BIT(2)
#define PSIHB_CR_FSP_IRQ_ENABLE PPC_BIT(3)
#define PSIHB_CR_FSP_ERR_RSP_ENABLE PPC_BIT(4)
#define PSIHB_CR_PSI_LINK_ENABLE PPC_BIT(5)
@@ -91,6 +86,7 @@
/* Secure version of CR for P8 and P9 (TCE enable bit) */
#define PSIHB_PHBSCR 0x90
+#define PSIHB_PHBSCR_TCE_ENABLE PPC_BIT(2)
/* P9 registers */