pau: link training

Add elementary functions to handle a phb complete, fundamental and
hot resets.
For the time being, specific creset and hreset are not supported.

A complete fundamental reset is based on the following steps, in this
order:
- Place all bricks into Fence state
- Disable BARs
- Reset ODL to Power-on Values
- Set the i2c reset pin in output mode
- Initialize PHY Lanes
- Deassert ODL reset
- Clear the the i2c reset pin
- Unfence bricks
- Enable BARs
- Enable ODL training mode

Link training is also set up.

Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>

3 files changed, 53 insertions, 0 deletions

diff --git a/include/pau-regs.h b/include/pau-regs.h
index b852a5b..7a5aaa5 100644
--- a/include/pau-regs.h
+++ b/include/pau-regs.h
@@ -142,6 +142,8 @@
 #define PAU_OTL_MISC_ERROR_SIG_RXI(brk)		(PAU_BLOCK_OTL(brk) + 0x070)
 #define PAU_OTL_MISC_ERROR_SIG_RXO(brk)		(PAU_BLOCK_OTL(brk) + 0x078)
 #define PAU_OTL_MISC_ERR_RPT_HOLD1(brk)		(PAU_BLOCK_OTL(brk) + 0x0B0)
+#define PAU_OTL_MISC_CFG_TX2(brk)		(PAU_BLOCK_OTL(brk) + 0x0C0)
+#define   PAU_OTL_MISC_CFG_TX2_SEND_EN		PPC_BIT(0)
 #define PAU_OTL_MISC_PSL_DSISR_AN(brk)		(PAU_BLOCK_OTL_PSL(brk) + 0x000)
 #define PAU_OTL_MISC_PSL_DAR_AN(brk)		(PAU_BLOCK_OTL_PSL(brk) + 0x008)
 #define PAU_OTL_MISC_PSL_TFC_AN(brk)		(PAU_BLOCK_OTL_PSL(brk) + 0x010)
@@ -178,6 +180,9 @@
 #define PAU_MISC_INT_1_CONFIG			(PAU_BLOCK_PAU_MISC + 0x068)
 #define PAU_MISC_INT_BAR			(PAU_BLOCK_PAU_MISC + 0x098)
 #define   PAU_MISC_INT_BAR_ADDR			PPC_BITMASK(0, 39)
+#define PAU_MISC_FENCE_STATE			(PAU_BLOCK_PAU_MISC + 0x0B0)
+#define   PAU_MISC_FENCE_STATE_CLEAR(brk)	PPC_BIT(0 + (brk))
+#define   PAU_MISC_FENCE_STATE_SET(brk)		PPC_BIT(12 + (brk))
 #define PAU_MISC_BDF2PE_CFG(n)			(PAU_BLOCK_PAU_MISC + 0x100 + (n) * 8)
 #define   PAU_MISC_BDF2PE_CFG_ENABLE		PPC_BIT(0)
 #define   PAU_MISC_BDF2PE_CFG_PE		PPC_BITMASK(4, 7)
diff --git a/include/pau.h b/include/pau.h
index 9fbccb8..c0a0940 100644
--- a/include/pau.h
+++ b/include/pau.h
@@ -40,6 +40,8 @@ struct pau_dev {
 	struct dt_node		*dn;
 	struct phb		phb;
 	uint32_t		status;
+	unsigned long		train_start;
+	unsigned long		train_timeout;
 
 	struct pau_bar		ntl_bar;
 	struct pau_bar		genid_bar;
diff --git a/include/xscom-p10-regs.h b/include/xscom-p10-regs.h
index 5ca4703..51fec51 100644
--- a/include/xscom-p10-regs.h
+++ b/include/xscom-p10-regs.h
@@ -58,4 +58,50 @@
 
 #define P10_ROOT_CONTROL_7		0x50017
 
+/* PB DLL Configuration Registers */
+#define P10_OB_ODL(ob)				(0x18011000 + (ob) * 0x1000000)
+
+#define P10_OB_ODL_PHY_CONFIG(ob)		(P10_OB_ODL(ob) + 0x0C)
+#define  P10_OB_ODL_PHY_CONFIG_LINK_SELECT	PPC_BITMASK(56, 57)
+#define  P10_OB_ODL_PHY_CONFIG_DL_SELECT	PPC_BITMASK(62, 63)
+
+#define P10_OB_ODL_PERF_MON_CONFIG(ob)		(P10_OB_ODL(ob) + 0x1C)
+#define   P10_OB_ODL_PERF_MON_CONFIG_ENABLE	PPC_BITMASK(0, 1)
+#define   P10_OB_ODL_PERF_MON_CONFIG_LINK0	0b10
+#define   P10_OB_ODL_PERF_MON_CONFIG_LINK1	0b01
+#define   P10_OB_ODL_PERF_MON_CONFIG_SIZE	PPC_BITMASK(16, 23)
+#define   P10_OB_ODL_PERF_MON_CONFIG_SIZE16	0xFF
+
+#define P10_OB_ODL_PERF_MON_SELECT(ob)		(P10_OB_ODL(ob) + 0x1D)
+#define   P10_OB_ODL_PERF_MON_SELECT_COUNTER	PPC_BITMASK(0, 7)
+#define   P10_OB_ODL_PERF_MON_SELECT_CRC_ODL	0x44
+#define   P10_OB_ODL_PERF_MON_SELECT_CRC_DLX	0x45
+
+#define P10_OB_PERF_COUNTER0(ob)		(P10_OB_ODL(ob) + 0x1E)
+#define   P10_OB_PERF_COUNTER0_LOW		PPC_BITMASK(0, 31)
+#define   P10_OB_PERF_COUNTER0_HIGH		PPC_BITMASK(32, 63)
+
+#define P10_OB_ODL_CONFIG(ob, brk)		(P10_OB_ODL(ob) + 0x2A + brk)
+#define   P10_OB_ODL_CONFIG_RESET		PPC_BIT(0)
+#define   P10_OB_ODL_CONFIG_VERSION		PPC_BITMASK(2, 7)
+#define   P10_OB_ODL_CONFIG_TRAIN_MODE		PPC_BITMASK(8, 11)
+#define   P10_OB_ODL_CONFIG_SUPPORTED_MODES	PPC_BITMASK(12, 15)
+#define   P10_OB_ODL_CONFIG_X4_BACKOFF_ENABLE	PPC_BIT(16)
+#define   P10_OB_ODL_CONFIG_PHY_CNTR_LIMIT	PPC_BITMASK(20, 23)
+#define   P10_OB_ODL_CONFIG_DEBUG_ENABLE	PPC_BIT(33)
+#define   P10_OB_ODL_CONFIG_FWD_PROGRESS_TIMER	PPC_BITMASK(40, 43)
+
+#define P10_OB_ODL_STATUS(ob, brk)		(P10_OB_ODL(ob) + 0x2C + brk)
+#define   P10_OB_ODL_STATUS_TRAINED_MODE	PPC_BITMASK(0, 3)
+#define   P10_OB_ODL_STATUS_RX_TRAINED_LANES	PPC_BITMASK(16, 23)
+#define   P10_OB_ODL_STATUS_TX_TRAINED_LANES	PPC_BITMASK(24, 31)
+#define   P10_OB_ODL_STATUS_TRAINING_STATE	PPC_BITMASK(49, 51)
+
+#define P10_OB_ODL_TRAIN_STAT(ob, brk)		(P10_OB_ODL(ob) + 0x2E + brk)
+#define   P10_OB_ODL_TRAIN_STAT_PATTERN_B	PPC_BITMASK(8, 15)
+
+#define P10_OB_ODL_DLX_INFO(ob, brk)		(P10_OB_ODL(ob) + 0x32 + brk)
+
+#define P10_OB_ODL_LINK_SPEED_STATUS(ob, brk)	(P10_OB_ODL(ob) + 0x34 + brk)
+
 #endif /* __XSCOM_P10_REGS_H__ */