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| author | Cédric Le Goater <clg@kaod.org> | 2019-10-01 09:00:02 +0200 |
|---|---|---|
| committer | Oliver O'Halloran <oohall@gmail.com> | 2019-11-04 10:52:47 +1100 |
| commit | 6214cb800db981d1944615da577dfa46ecf3bfb8 (patch) | |
| tree | c18703119fa9a1c7e4b32ce17cbb3a586d815384 /include | |
| parent | 2354857fcae538867c19d0f108da2e82c1a43001 (diff) | |
| download | skiboot-6214cb800db981d1944615da577dfa46ecf3bfb8.zip skiboot-6214cb800db981d1944615da577dfa46ecf3bfb8.tar.gz skiboot-6214cb800db981d1944615da577dfa46ecf3bfb8.tar.bz2 | |
xive/p9: introduce the ESB magic MMIO offsets
The following offsets into the ESB MMIO allow to read or manipulate
the PQ bits. They must be used with an 8-byte load instruction. They
all return the previous state of the interrupt (atomically).
Additionally, some ESB pages support doing an EOI via a store and
some ESBs support doing a trigger via a separate trigger page.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/xive-regs.h | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/include/xive-regs.h b/include/xive-regs.h index 2d72866..a6a6ce3 100644 --- a/include/xive-regs.h +++ b/include/xive-regs.h @@ -86,4 +86,23 @@ #define TM_QW3_NSR_I PPC_BIT8(2) #define TM_QW3_NSR_GRP_LVL PPC_BIT8(3,7) +/* + * "magic" Event State Buffer (ESB) MMIO offsets. + * + * The following offsets into the ESB MMIO allow to read or manipulate + * the PQ bits. They must be used with an 8-byte load instruction. + * They all return the previous state of the interrupt (atomically). + * + * Additionally, some ESB pages support doing an EOI via a store and + * some ESBs support doing a trigger via a separate trigger page. + */ +#define XIVE_ESB_STORE_TRIGGER 0x000 /* Store in range 0x000-0x3FF */ +#define XIVE_ESB_STORE_EOI 0x400 /* Store */ +#define XIVE_ESB_LOAD_EOI 0x000 /* Load */ +#define XIVE_ESB_GET 0x800 /* Load */ +#define XIVE_ESB_SET_PQ_00 0xc00 /* Load */ +#define XIVE_ESB_SET_PQ_01 0xd00 /* Load */ +#define XIVE_ESB_SET_PQ_10 0xe00 /* Load */ +#define XIVE_ESB_SET_PQ_11 0xf00 /* Load */ + #endif /* XIVE_REGS_H__ */ |