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| author | Nicholas Piggin <npiggin@gmail.com> | 2019-11-11 15:44:48 +1000 |
|---|---|---|
| committer | Oliver O'Halloran <oohall@gmail.com> | 2019-11-11 18:35:00 +1100 |
| commit | 3fbfb0e351cdeb9279aa2857046ecf0823b787dc (patch) | |
| tree | eb1564eaf99f4dbb1d21c6be55e813d3eafa0d83 /include | |
| parent | bb445088d0dd11c2a1b749792e49ccdb1d6f6c33 (diff) | |
| download | skiboot-3fbfb0e351cdeb9279aa2857046ecf0823b787dc.zip skiboot-3fbfb0e351cdeb9279aa2857046ecf0823b787dc.tar.gz skiboot-3fbfb0e351cdeb9279aa2857046ecf0823b787dc.tar.bz2 | |
Remove dead POWER7 code
There are a number of proc_gen branches removed that are trivially
dead code and comments that refer to P7. As well as those:
- Oliver points out that add_xics_icps() must be unused on POWER8
because it asserts if number of threads > 4, so remove it.
- Change 16b7ae641 ("Remove POWER7 and POWER7+ support") removed all
references to opal_boot_trampoline, so remove that.
- It also removed the only non-trival choose_bus implementation, so
that is removed and its caller simplified.
- Remove the paca code, later CPUs use pcia.
Cc: Stewart Smith <stewart@flamingspork.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/chip.h | 4 | ||||
| -rw-r--r-- | include/mem-map.h | 2 | ||||
| -rw-r--r-- | include/nx.h | 2 | ||||
| -rw-r--r-- | include/pci.h | 6 |
4 files changed, 3 insertions, 11 deletions
diff --git a/include/chip.h b/include/chip.h index adb962a..f14e78b 100644 --- a/include/chip.h +++ b/include/chip.h @@ -34,9 +34,7 @@ * | | | * |___|___|___|___|___|___| * - * The difference with P7 is the absence of T bit, the ChipID - * is 3 bits long. The GCID is thus the same as the high bits - * if the PIR + * The the ChipID is 3 bits long, the GCID is the same as the high bits of PIR */ #define P8_PIR2GCID(pir) (((pir) >> 7) & 0x3f) diff --git a/include/mem-map.h b/include/mem-map.h index 9914651..61ecac3 100644 --- a/include/mem-map.h +++ b/include/mem-map.h @@ -99,7 +99,7 @@ /* This is our PSI TCE table. It's 256K entries on P8 */ #define PSI_TCE_TABLE_BASE (SKIBOOT_BASE + 0x01a00000) -#define PSI_TCE_TABLE_SIZE_P8 0x00200000UL +#define PSI_TCE_TABLE_SIZE 0x00200000UL /* This is our dump result table after MPIPL. Hostboot will write to this * memory after moving memory content from source to destination memory. diff --git a/include/nx.h b/include/nx.h index 675d17a..4950a2d 100644 --- a/include/nx.h +++ b/include/nx.h @@ -86,7 +86,7 @@ #define NX_EE_CFG_CH7 PPC_BIT(53) /* AMF */ #define NX_EE_CFG_CH6 PPC_BIT(54) /* AMF */ #define NX_EE_CFG_CH5 PPC_BIT(55) /* AMF */ -#define NX_EE_CFG_CH4 PPC_BIT(56) /* P7: SYM, P8: AMF */ +#define NX_EE_CFG_CH4 PPC_BIT(56) /* AMF */ #define NX_EE_CFG_CH3 PPC_BIT(57) /* SYM */ #define NX_EE_CFG_CH2 PPC_BIT(58) /* SYM */ #define NX_P9_EE_CFG_CH4 PPC_BIT(61) /* gzip */ diff --git a/include/pci.h b/include/pci.h index 8169fe6..fb91d79 100644 --- a/include/pci.h +++ b/include/pci.h @@ -218,12 +218,6 @@ struct phb_ops { int64_t (*cfg_write32)(struct phb *phb, uint32_t bdfn, uint32_t offset, uint32_t data); - /* - * Bus number selection. See pci_scan() for a description - */ - uint8_t (*choose_bus)(struct phb *phb, struct pci_device *bridge, - uint8_t candidate, uint8_t *max_bus, - bool *use_max); int64_t (*get_reserved_pe_number)(struct phb *phb); /* |