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| author | Vasant Hegde <hegdevasant@linux.vnet.ibm.com> | 2019-07-12 16:47:54 +0530 |
|---|---|---|
| committer | Oliver O'Halloran <oohall@gmail.com> | 2019-08-15 17:53:56 +1000 |
| commit | aa694ea08c0d6350455400e69d266f1dada062c1 (patch) | |
| tree | a534a1ddf411b6a1c5b00f72f23431965ffacbbb /include | |
| parent | fbd875d77f30ee9a713625c3f4400cde06e70ac8 (diff) | |
| download | skiboot-aa694ea08c0d6350455400e69d266f1dada062c1.zip skiboot-aa694ea08c0d6350455400e69d266f1dada062c1.tar.gz skiboot-aa694ea08c0d6350455400e69d266f1dada062c1.tar.bz2 | |
HIOMAP: Reset bmc mbox in MPIPL path
During boot SBE and early hostboot does not use HIOMAP protocol to get image
from PNOR. Instead it expects PNOR TOC and Hostboot Boot Loader to be
available at particular address in LPC bus. mbox daemon in BMC side takes
care of this during normal boot. Once boot is complete mbox daemon switches
to normal mode.
During normal reboot, BMC side mbox daemon gets notification and takes care of
loading PNOR TOC and HBBL to LPC bus again.
In MPIPL path, OPAL calls SBE S0 interrupt to initiate MPIPL. BMC will not be
aware of this. But SBE expects PNOR TOC and HBBL to be available in LPC bus at
predefined address. Hence call HIOMAP Reset from OPAL in assert path.
This needs working LPC and IPMI driver in OPAL. If we have issue in these
drivers then we may not be able to reset BMC MBOX properly. Hence MPIPL may
fail. We have to live with this until we find a way to intiate BMC on MPIPL.
CC: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
[oliver: rebased]
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/skiboot.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/skiboot.h b/include/skiboot.h index 6cac1cf..e554325 100644 --- a/include/skiboot.h +++ b/include/skiboot.h @@ -212,6 +212,7 @@ extern int flash_start_preload_resource(enum resource_id id, uint32_t subid, extern int flash_resource_loaded(enum resource_id id, uint32_t idx); extern bool flash_reserve(void); extern void flash_release(void); +extern bool flash_unregister(void); #define FLASH_SUBPART_ALIGNMENT 0x1000 #define FLASH_SUBPART_HEADER_SIZE FLASH_SUBPART_ALIGNMENT extern int flash_subpart_info(void *part_header, uint32_t header_len, |