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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2014-10-08 14:10:28 +1100
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2014-10-08 14:10:28 +1100
commit1b73ac736790f9aa951d855f6bdb9380437a6da8 (patch)
tree1b4bbf1b8f07392b64e6df2a229c9a602c93d295 /include
parent8f5e2af818e913c619054e2e7e265a68b258f9c4 (diff)
parentcdbca5395253f162cdd6ca2de6482b9bd9230bb7 (diff)
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Merge branch 'release-2.1.1'
Diffstat (limited to 'include')
-rw-r--r--include/opal.h54
-rw-r--r--include/pci.h4
-rw-r--r--include/phb3-regs.h6
3 files changed, 34 insertions, 30 deletions
diff --git a/include/opal.h b/include/opal.h
index fb0cee4..acb2bb5 100644
--- a/include/opal.h
+++ b/include/opal.h
@@ -131,7 +131,7 @@
#define OPAL_PCI_SET_PHB_CAPI_MODE 93
#define OPAL_DUMP_INFO2 94
#define OPAL_WRITE_OPPANEL_ASYNC 95
-#define OPAL_PCI_ERR_INJCT 96
+#define OPAL_PCI_ERR_INJECT 96
#define OPAL_PCI_EEH_FREEZE_SET 97
#define OPAL_HANDLE_HMI 98
#define OPAL_CONFIG_CPU_IDLE_STATE 99
@@ -191,31 +191,33 @@ enum OpalPciErrorSeverity {
OPAL_EEH_SEV_INF = 5
};
-enum OpalErrinjctType {
- OpalErrinjctTypeIoaBusError = 0,
- OpalErrinjctTypeIoaBusError64 = 1,
-
- /* IoaBusError & IoaBusError64 */
- OpalEjtIoaLoadMemAddr = 0,
- OpalEjtIoaLoadMemData = 1,
- OpalEjtIoaLoadIoAddr = 2,
- OpalEjtIoaLoadIoData = 3,
- OpalEjtIoaLoadConfigAddr = 4,
- OpalEjtIoaLoadConfigData = 5,
- OpalEjtIoaStoreMemAddr = 6,
- OpalEjtIoaStoreMemData = 7,
- OpalEjtIoaStoreIoAddr = 8,
- OpalEjtIoaStoreIoData = 9,
- OpalEjtIoaStoreConfigAddr = 10,
- OpalEjtIoaStoreConfigData = 11,
- OpalEjtIoaDmaReadMemAddr = 12,
- OpalEjtIoaDmaReadMemData = 13,
- OpalEjtIoaDmaReadMemMaster = 14,
- OpalEjtIoaDmaReadMemTarget = 15,
- OpalEjtIoaDmaWriteMemAddr = 16,
- OpalEjtIoaDmaWriteMemData = 17,
- OpalEjtIoaDmaWriteMemMaster = 18,
- OpalEjtIoaDmaWriteMemTarget = 19,
+enum OpalErrinjectType {
+ OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR = 0,
+ OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64 = 1,
+};
+
+enum OpalErrinjectFunc {
+ /* IOA bus specific errors */
+ OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR = 0,
+ OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_DATA = 1,
+ OPAL_ERR_INJECT_FUNC_IOA_LD_IO_ADDR = 2,
+ OPAL_ERR_INJECT_FUNC_IOA_LD_IO_DATA = 3,
+ OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_ADDR = 4,
+ OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_DATA = 5,
+ OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_ADDR = 6,
+ OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_DATA = 7,
+ OPAL_ERR_INJECT_FUNC_IOA_ST_IO_ADDR = 8,
+ OPAL_ERR_INJECT_FUNC_IOA_ST_IO_DATA = 9,
+ OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_ADDR = 10,
+ OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_DATA = 11,
+ OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_ADDR = 12,
+ OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_DATA = 13,
+ OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_MASTER = 14,
+ OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_TARGET = 15,
+ OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_ADDR = 16,
+ OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_DATA = 17,
+ OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_MASTER = 18,
+ OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET = 19,
};
enum OpalShpcAction {
diff --git a/include/pci.h b/include/pci.h
index c15935c..9573961 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -257,8 +257,8 @@ struct phb_ops {
uint64_t eeh_action_token);
int64_t (*eeh_freeze_set)(struct phb *phb, uint64_t pe_number,
uint64_t eeh_action_token);
- int64_t (*err_injct)(struct phb *phb, uint32_t pe_no, uint32_t type,
- uint32_t function, uint64_t addr, uint64_t mask);
+ int64_t (*err_inject)(struct phb *phb, uint32_t pe_no, uint32_t type,
+ uint32_t func, uint64_t addr, uint64_t mask);
int64_t (*get_diag_data)(struct phb *phb, void *diag_buffer,
uint64_t diag_buffer_len);
int64_t (*get_diag_data2)(struct phb *phb, void *diag_buffer,
diff --git a/include/phb3-regs.h b/include/phb3-regs.h
index 2611b5f..686a113 100644
--- a/include/phb3-regs.h
+++ b/include/phb3-regs.h
@@ -144,11 +144,13 @@
#define PHB_PAPR_ERR_INJ_CTL_WR PPC_BIT(5)
#define PHB_PAPR_ERR_INJ_CTL_FREEZE PPC_BIT(6)
#define PHB_PAPR_ERR_INJ_ADDR 0x2b8
+#define PHB_PAPR_ERR_INJ_ADDR_MMIO_MASK PPC_BITMASK(16,63)
+#define PHB_PAPR_ERR_INJ_ADDR_MMIO_LSH PPC_BITLSHIFT(63)
#define PHB_PAPR_ERR_INJ_MASK 0x2c0
#define PHB_PAPR_ERR_INJ_MASK_CFG_MASK PPC_BITMASK(4,11)
#define PHB_PAPR_ERR_INJ_MASK_CFG_LSH PPC_BITLSHIFT(11)
-#define PHB_PAPR_ERR_INJ_MASK_MMIO_MASK PPC_BITMASK(14,40) /* 8M aligned */
-#define PHB_PAPR_ERR_INJ_MASK_MMIO_LSH PPC_BITLSHIFT(40)
+#define PHB_PAPR_ERR_INJ_MASK_MMIO_MASK PPC_BITMASK(16,63)
+#define PHB_PAPR_ERR_INJ_MASK_MMIO_LSH PPC_BITLSHIFT(63)
#define PHB_ETU_ERR_SUMMARY 0x2c8
/* UTL registers */