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| author | Andrew Donnellan <ajd@linux.ibm.com> | 2019-05-14 11:10:33 +1000 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.ibm.com> | 2019-05-20 14:20:29 +1000 |
| commit | 1a548857ce1f02f43585b326a891eed18a7b43b3 (patch) | |
| tree | 1032e9242e08254bb1264c77624e59470bc0580b /include | |
| parent | a00971e1946bf184c2f38e16123bdb3537602a9c (diff) | |
| download | skiboot-1a548857ce1f02f43585b326a891eed18a7b43b3.zip skiboot-1a548857ce1f02f43585b326a891eed18a7b43b3.tar.gz skiboot-1a548857ce1f02f43585b326a891eed18a7b43b3.tar.bz2 | |
hw/npu2-opencapi: Add initial support for allocating OpenCAPI LPC memory
Lowest Point of Coherency (LPC) memory allows the host to access memory on
an OpenCAPI device.
Define 2 OPAL calls, OPAL_NPU_MEM_ALLOC and OPAL_NPU_MEM_RELEASE, for
assigning and clearing the memory BAR. (We try to avoid using the term
"LPC" to avoid confusion with Low Pin Count.)
At present, we use a fixed location in the address space, which means we
are restricted to a single range of 4TB, on a single OpenCAPI device per
chip. In future, we'll use some chip ID extension magic to give us more
space, and some sort of allocator to assign ranges to more than one device.
Signed-off-by: Andrew Donnellan <ajd@linux.ibm.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/npu2-regs.h | 7 | ||||
| -rw-r--r-- | include/npu2.h | 11 | ||||
| -rw-r--r-- | include/opal-api.h | 4 | ||||
| -rw-r--r-- | include/phys-map.h | 1 |
4 files changed, 19 insertions, 4 deletions
diff --git a/include/npu2-regs.h b/include/npu2-regs.h index 61e8ea8..3cb587a 100644 --- a/include/npu2-regs.h +++ b/include/npu2-regs.h @@ -239,6 +239,13 @@ void npu2_scom_write(uint64_t gcid, uint64_t scom_base, #define NPU2_CQ_CTL_STATUS 0x090 #define NPU2_CQ_CTL_STATUS_BRK0_AM_FENCED PPC_BITMASK(48, 49) #define NPU2_CQ_CTL_STATUS_BRK1_AM_FENCED PPC_BITMASK(50, 51) +#define NPU2_CQ_CTL_MISC_PA0_CONFIG 0x0A0 /* or should that be CS */ +#define NPU2_CQ_CTL_MISC_PA1_CONFIG 0x0A8 /* or should that be CS */ +#define NPU2_CQ_CTL_MISC_PA_CONFIG_MEMSELMATCH PPC_BITMASK(0,2) +#define NPU2_CQ_CTL_MISC_PA_CONFIG_GRANULE PPC_BIT(3) +#define NPU2_CQ_CTL_MISC_PA_CONFIG_SIZE PPC_BITMASK(4,7) +#define NPU2_CQ_CTL_MISC_PA_CONFIG_MODE PPC_BITMASK(8,11) +#define NPU2_CQ_CTL_MISC_PA_CONFIG_MASK PPC_BITMASK(13,19) #define NPU2_CQ_C_ERR_RPT_MSG0 0x0C0 #define NPU2_CQ_C_ERR_RPT_MSG1 0x0C8 #define NPU2_CQ_C_ERR_RPT_FIRST0 0x0D0 diff --git a/include/npu2.h b/include/npu2.h index d58aab4..5b2a436 100644 --- a/include/npu2.h +++ b/include/npu2.h @@ -180,8 +180,10 @@ struct npu2 { uint64_t tve_cache[16]; bool tx_zcal_complete[2]; - /* Used to protect global MMIO space, in particular the XTS - * tables. */ + /* + * Used to protect global MMIO space, in particular the XTS + * tables, and LPC allocation + */ struct lock lock; /* NVLink */ @@ -193,6 +195,11 @@ struct npu2 { struct lock i2c_lock; uint8_t i2c_pin_mode; uint8_t i2c_pin_wr_state; + /* + * Which device currently has an LPC allocation. + * Temporary as long as we only support 1 LPC alloc per chip. + */ + struct npu2_dev *lpc_mem_allocated; }; static inline struct npu2 *phb_to_npu2_nvlink(struct phb *phb) diff --git a/include/opal-api.h b/include/opal-api.h index e461c9d..b0ad435 100644 --- a/include/opal-api.h +++ b/include/opal-api.h @@ -227,8 +227,8 @@ #define OPAL_NPU_SET_RELAXED_ORDER 168 #define OPAL_NPU_GET_RELAXED_ORDER 169 #define OPAL_XIVE_GET_VP_STATE 170 /* Get NVT state */ -#define OPAL_NPU_RESERVED1 171 /* LPC Allocate */ -#define OPAL_NPU_RESERVED2 172 /* LPC Release */ +#define OPAL_NPU_MEM_ALLOC 171 +#define OPAL_NPU_MEM_RELEASE 172 #define OPAL_LAST 172 #define QUIESCE_HOLD 1 /* Spin all calls at entry */ diff --git a/include/phys-map.h b/include/phys-map.h index 73adda0..0cf48b6 100644 --- a/include/phys-map.h +++ b/include/phys-map.h @@ -28,6 +28,7 @@ enum phys_map_type { SYSTEM_MEM, GPU_MEM_4T_DOWN, GPU_MEM_4T_UP, + OCAPI_MEM, PHB4_64BIT_MMIO, PHB4_32BIT_MMIO, PHB4_XIVE_ESB, |