Remove POWER7 and POWER7+ support

It's been a good long while since either OPAL POWER7 user touched a
machine, and even longer since they'd have been okay using an old
version rather than tracking master.

There's also been no testing of OPAL on POWER7 systems for an awfully
long time, so it's pretty safe to assume that it's very much bitrotted.

It also saves a whole 14kb of xz compressed payload space.

Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
Enthusiasticly-Acked-by: Oliver O'Halloran <oohall@gmail.com>
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>

11 files changed, 8 insertions, 1189 deletions

diff --git a/include/chip.h b/include/chip.h
index 5231d17..f94149b 100644
--- a/include/chip.h
+++ b/include/chip.h
@@ -31,31 +31,11 @@
  * This ID is the HW fabric ID of a chip based on the XSCOM numbering,
  * also known as "GCID" (Global Chip ID).
  *
- * The format of this number is different between P7 and P8 and care must
+ * The format of this number is different between chip generations and care must
  * be taken when trying to convert between this chip ID and some other
  * representation such as PIR values, interrupt-server numbers etc... :
  *
- * P7 GCID
- * -------
- *
- * Global chip ID is a 6 bit number:
- *
- *     NodeID    T   ChipID
- * |           |   |       |
- * |___|___|___|___|___|___|
- *
- * Where T is the "torrent" bit and is 0 for P7 chips and 1 for
- * directly XSCOM'able IO chips such as Torrent
- *
- * This macro converts a PIR to a GCID
  */
-#define P7_PIR2GCID(pir) ({ 				\
-	uint32_t _pir = pir;				\
-	((_pir >> 4) & 0x38) | ((_pir >> 5) & 0x3); })
-
-#define P7_PIR2COREID(pir) (((pir) >> 2) & 0x7)
-
-#define P7_PIR2THREADID(pir) ((pir) & 0x3)
 
 /*
  * P8 GCID
@@ -119,8 +99,6 @@ struct p9_dio;
 /* Chip type */
 enum proc_chip_type {
 	PROC_CHIP_UNKNOWN,
-	PROC_CHIP_P7,
-	PROC_CHIP_P7P,
 	PROC_CHIP_P8_MURANO,
 	PROC_CHIP_P8_VENICE,
 	PROC_CHIP_P8_NAPLES,
diff --git a/include/gx.h b/include/gx.h
deleted file mode 100644
index 4ba1661..0000000
--- a/include/gx.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/* Copyright 2013-2014 IBM Corp.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * 	http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
- * implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/*
- * Definitions relative to the P7 and P7+ GX controller
- */
-#ifndef __GX_H
-#define __GX_H
-
-#include <bitutils.h>
-
-/* P7 GX Mode 1 register (contains PSI BUID) */
-#define GX_P7_MODE1_REG		0x0201180A
-#define GX_P7_MODE1_PSI_BUID		PPC_BITMASK(18,26)
-#define GX_P7_MODE1_PSI_BUID_DISABLE	PPC_BIT(27)
-
-/* P7+ GX Mode 4 register (PSI and NX BUIDs ) */
-#define GX_P7P_MODE4_REG	0x02011811
-#define GX_P7P_MODE4_ENABLE_NX_BUID	PPC_BIT(0)
-#define GX_P7P_MODE4_NX_BUID_BASE	PPC_BITMASK(1,9)
-#define GX_P7P_MODE4_NX_BUID_MASK	PPC_BITMASK(10,18)
-#define GX_P7P_MODE4_PSI_BUID		PPC_BITMASK(19,27)
-#define GX_P7P_MODE4_PSI_BUID_DISABLE	PPC_BIT(28)
-
-/* P7 GX TCE BAR and mask */
-#define GX_P7_GX0_TCE_BAR	0x02011845
-#define GX_P7_TCE_BAR_ADDR		PPC_BITMASK(0,25)
-#define GX_P7_TCE_BAR_ADDR_SHIFT	PPC_BITLSHIFT(43)
-#define GX_P7_TCE_BAR_ENABLE		PPC_BIT(26)
-#define GX_P7_GX0_TCE_MASK	0x0201184B
-#define GX_P7_TCE_MASK			PPC_BITMASK(0,25)
-#define GX_P7_GX1_TCE_BAR	0x02011885
-#define GX_P7_GX1_TCE_MASK	0x0201188B
-
-
-extern int gx_configure_psi_buid(uint32_t chip, uint32_t buid);
-extern int gx_configure_tce_bar(uint32_t chip, uint32_t gx, uint64_t addr,
-				uint64_t size);
-
-#endif /* __GX_H */
diff --git a/include/interrupts.h b/include/interrupts.h
index 2c4fa7e..7024fac 100644
--- a/include/interrupts.h
+++ b/include/interrupts.h
@@ -20,128 +20,6 @@
 #include <stdint.h>
 #include <ccan/list/list.h>
 
-/*
- * Note about interrupt numbers on P7/P7+
- * ======================================
- *
- * The form of an interrupt number in the system on P7/P7+ is as follow:
- *
- * |  Node  | T| Chip|GX|           BUID           |   Level   |
- * |--|--|--|--|--|--|--|--|--|--|--|--|--|--|--|--|--|--|--|--|
- *
- * Where:
- *
- *  - Node   : The 3-bit node number
- *  - T      : 1 for a Torrent chip, 0 otherwise
- *  - Chip   : 2-bit chip number in a node
- *  - GX     : GX bus identifier
- *  - BUID   : Bus identifier (*)
- *  - Level  : Interrupt number
- *
- * (*) The BUID/Level distinction is mostly historical, interrupt
- *     controllers such as the ICS in the PHBs "use" some of the
- *     low BUID bits as an extension to the interrupt number
- *
- * The NodeID and ChipID together form a 5-bit Processor Chip ID as
- * found in the PIR or in the SPIRA data structures (without the T bit)
- *
- * PSI interrupt numbering scheme:
- * -------------------------------
- *
- * This is tentatively deduced from stuff I found in some SCOM regs
- * and in the BookIV. The PSIHB can be used to specify the 9-bit BUID,
- * the Level is always 0. The doc also says that it prepends the 6-bit
- * PowerBus chipID (Node + T + Chip). I *assume* that it also prepends
- * a 0 in place of the GX bit.
- *
- * OPAL seems to be arbitrarily using a BUID value of 0x3, I shall do
- * the same "just in case" :-)
- *
- * NOTE: From grep'ing around the giant SCOM file for "Build", I found
- *       what looks like a register in the GX controller (Mode1
- *       register) where the PSI BUID can be stored as well. From
- *       looking around with the FSP getscom command, it appears
- *       that both pHyp and OPAL set this consistently to the same
- *       value that appears in the PHB configuration.
- *
- * => This is confirmed. The NX needs a similar configuration, this
- *    tells the GX controller not to forward transactions for these
- *    BUIDs down the GX bus.
- *
- * PCI interrupt numbering scheme:
- * -------------------------------
- *
- * See IOCs
- *
- * NX interrupt numbering scheme (p7+):
- * ------------------------------------
- *
- * TBD
- *
- * 
- * Additional note about routing of interrupts in P7 and P7+
- * =========================================================
- *
- * There are two on-chip sources of interrupts on these that need a
- * special treatment: The PSI interrupt and the NX interrupts.
- *
- * The problem is that they use the same BUID space as the IO chips
- * connected to the GX bus, so the GX controller needs to be told
- * about these BUIDs in order to avoid forwarding them down the GX
- * link (and possibly choking due to the lack of reply).
- *
- * The bad news is that it's all undocumented. The good news is that
- * I found the info after chatting with Bill Daly (HW design) and
- * looking at the SCOM register maps.
- *
- * The way to set that up differs between P7 and P7+:
- *
- * - On P7, it's in the GX_MODE1 register at SCOM 0x0201180A, which
- *   among other things, contains those bits:
- *
- *     18:26 PSI_BUID: BUID to be used to indicate the interrupt is
- *                     for the PSI
- *        27 DISABLE_PSI_BUID: set to 1 to disable the buid reservation
- *                             for PSI
- *
- *   So one must write the 9-bit BUID (without the top chipID) of the
- *   PSI interrupt in there and clear the disable bit.
- *
- * - On P7+ it's in the GX_MODE4 register at SCOM 0x02011811
- *
- *         0 ENABLE_NX_BUID: set to 1 to enable the buid reservation for nx
- *       1:9 NX_BUID_BASE: BUID BASE to be used to indicate the interrupt
- *                         is for the nx
- *     10:18 NX_BUID_MASK: BUID mask for the nx buid base
- *     19:27 PSI_BUID: BUID to be used to indicate the interrupt is for
- *                     the PSI
- *        28 DISABLE_PSI_BUID: set to 1 to disable the buid reservation
- *                             for PSI
- *
- * Note: The NX_BUID_MASK should have bits set to 1 that are relevant for
- *       the comparison to NX_BUID_BASE, ie 4 interrupts means a mask
- *       value of b'111111100
- */
-
-#define P7_PSI_IRQ_BUID	0x3	/* 9-bit BUID for the PSI interrupts */
-
-/* Extract individual components of an IRQ number */
-#define P7_IRQ_BUID(irq)	(((irq) >>  4) & 0x1ff)
-#define P7_IRQ_GXID(irq)	(((irq) >> 13) & 0x1)
-#define P7_IRQ_CHIP(irq)	(((irq) >> 14) & 0x3)
-#define P7_IRQ_TBIT(irq)	(((irq) >> 16) & 0x1)
-#define P7_IRQ_NODE(irq)	(((irq) >> 17) & 0x7)
-
-/* Extract the "full BUID" (extension + BUID) */
-#define P7_IRQ_FBUID(irq)	(((irq) >> 4) & 0xffff)
-
-/* BUID Extension (GX + CHIP + T + NODE) */
-#define P7_IRQ_BEXT(irq)	(((irq) >> 13) & 0x7f)
-
-/* Strip extension from BUID */
-#define P7_BUID_BASE(buid)	((buid) & 0x1ff)
-
-
 /* Note about interrupt numbers on P8
  * ==================================
  *
diff --git a/include/mem-map.h b/include/mem-map.h
index fa5cacb..fc535e5 100644
--- a/include/mem-map.h
+++ b/include/mem-map.h
@@ -94,11 +94,8 @@
 #define SPIRA_HEAP_BASE		(SKIBOOT_BASE + 0x01200000)
 #define SPIRA_HEAP_SIZE		0x00800000
 
-/* This is our PSI TCE table. It's 16K entries on P7 and 256K
- * entries on P8
- */
+/* This is our PSI TCE table. It's 256K entries on P8 */
 #define PSI_TCE_TABLE_BASE	(SKIBOOT_BASE + 0x01a00000)
-#define PSI_TCE_TABLE_SIZE_P7	0x00020000UL
 #define PSI_TCE_TABLE_SIZE_P8	0x00200000UL
 
 /* Total size of the above area
diff --git a/include/nx.h b/include/nx.h
index 0322349..dcaf20f 100644
--- a/include/nx.h
+++ b/include/nx.h
@@ -21,15 +21,12 @@
 /* Register addresses and bit fields */
 /*************************************/
 
-#define NX_P7_SAT(sat, offset)	XSCOM_SAT(0x1, sat, offset)
 #define NX_P8_SAT(sat, offset)	XSCOM_SAT(0xc, sat, offset)
 #define NX_P9_SAT(sat, offset)	XSCOM_SAT(0x4, sat, offset)
 
 /* Random Number Generator */
-#define NX_P7_RNG_BAR		NX_P7_SAT(0x2, 0x0c)
 #define NX_P8_RNG_BAR		NX_P8_SAT(0x2, 0x0d)
 #define NX_P9_RNG_BAR		NX_P9_SAT(0x2, 0x0d)
-#define   NX_P7_RNG_BAR_ADDR		PPC_BITMASK(18, 51)
 #define   NX_P8_RNG_BAR_ADDR		PPC_BITMASK(14, 51)
 /*
  * Section 5.30 of P9 NX Workbook Version 2.42 shows RNG BAR as:
@@ -44,12 +41,10 @@
 #define   NX_RNG_BAR_SIZE		PPC_BITMASK(53, 55)
 #define   NX_RNG_BAR_ENABLE		PPC_BIT(52)
 
-#define NX_P7_RNG_CFG		NX_P7_SAT(0x2, 0x12)
 #define NX_P8_RNG_CFG		NX_P8_SAT(0x2, 0x12)
 #define   NX_RNG_CFG_ENABLE		PPC_BIT(63)
 
 /* Symmetric Crypto */
-#define NX_P7_SYM_CFG		NX_P7_SAT(0x2, 0x09)
 #define NX_P8_SYM_CFG		NX_P8_SAT(0x2, 0x0a)
 #define   NX_SYM_CFG_CI			PPC_BITMASK(2, 14)
 #define   NX_SYM_CFG_CT			PPC_BITMASK(18, 23)
@@ -57,15 +52,13 @@
 #define   NX_SYM_CFG_ENABLE		PPC_BIT(63)
 
 /* Asymmetric Crypto */
-#define NX_P7_ASYM_CFG		NX_P7_SAT(0x2, 0x0a)
 #define NX_P8_ASYM_CFG		NX_P8_SAT(0x2, 0x0b)
 #define   NX_ASYM_CFG_CI		PPC_BITMASK(2, 14)
 #define   NX_ASYM_CFG_CT		PPC_BITMASK(18, 23)
 #define   NX_ASYM_CFG_FC_ENABLE		PPC_BITMASK(32, 52)
 #define   NX_ASYM_CFG_ENABLE		PPC_BIT(63)
 
-/* 842 Compression. CFG is used only on P7+ and P8 */
-#define NX_P7_842_CFG		NX_P7_SAT(0x2, 0x0b)
+/* 842 Compression. CFG is used only on P8 */
 #define NX_P8_842_CFG		NX_P8_SAT(0x2, 0x0c)
 #define   NX_842_CFG_CI			PPC_BITMASK(2, 14)
 #define   NX_842_CFG_CT			PPC_BITMASK(18, 23)
@@ -73,7 +66,6 @@
 #define   NX_842_CFG_ENABLE		PPC_BIT(63)
 
 /* DMA */
-#define NX_P7_DMA_CFG		NX_P7_SAT(0x1, 0x02)
 #define NX_P8_DMA_CFG		NX_P8_SAT(0x1, 0x02)
 #define NX_P9_DMA_CFG		NX_P9_SAT(0x1, 0x02)
 #define   NX_DMA_CFG_GZIP_COMPRESS_MAX_RR	PPC_BITMASK(8, 11)
@@ -101,7 +93,6 @@
 #define   NX_DMA_CFG_842_OUTPUT_DATA_WR		PPC_BIT(63)
 
 /* Engine Enable Register */
-#define NX_P7_EE_CFG		NX_P7_SAT(0x1, 0x01)
 #define NX_P8_EE_CFG		NX_P8_SAT(0x1, 0x01)
 #define NX_P9_EE_CFG		NX_P9_SAT(0x1, 0x01)
 #define   NX_EE_CFG_EFUSE		PPC_BIT(0)
@@ -123,7 +114,6 @@
 #define   NX_P9_DMA_VAS_MMIO_ADDR		PPC_BITMASK(8, 38)
 
 /* PowerBus Registers */
-#define NX_P7_CRB_IQ		NX_P7_SAT(0x2, 0x0e)
 #define NX_P8_CRB_IQ		NX_P8_SAT(0x2, 0x0f)
 #define   NX_CRB_IQ_SYM			PPC_BITMASK(0, 2)
 #define   NX_CRB_IQ_ASYM		PPC_BITMASK(3, 5)
@@ -165,7 +155,6 @@
 #define NX_P9_ERAT_STATUS_CTRL			NX_P9_SAT(0x3, 0x16)
 
 /* NX Status Register */
-#define NX_P7_STATUS		NX_P7_SAT(0x1, 0x00)
 #define NX_P8_STATUS		NX_P8_SAT(0x1, 0x00)
 #define NX_P9_STATUS		NX_P9_SAT(0x1, 0x00) /* DMA Status register */
 #define   NX_STATUS_HMI_ACTIVE		PPC_BIT(54)
@@ -180,10 +169,8 @@
 #define   NX_STATUS_DMA_CH7_IDLE	PPC_BIT(63)
 
 /* Channel Status Registers */
-#define NX_P7_CH_CRB(ch)	NX_P7_SAT(0x1, 0x03 + ((ch) * 2))
 #define NX_P8_CH_CRB(ch)	NX_P8_SAT(0x1, 0x03 + ((ch) * 2))
 #define NX_P9_CH_CRB(ch)	NX_P9_SAT(0x1, 0x03 + ((ch) * 2))
-#define NX_P7_CH_STATUS(ch)	NX_P7_SAT(0x1, 0x04 + ((ch) * 2))
 #define NX_P8_CH_STATUS(ch)	NX_P8_SAT(0x1, 0x04 + ((ch) * 2))
 #define   NX_CH_STATUS_ABORT		PPC_BIT(0)
 #define   NX_CH_STATUS_CCB_VALID	PPC_BIT(4)
@@ -196,7 +183,6 @@
 #define   NX_CH_STATUS_CRB_SJT		PPC_BITMASK(50, 63)
 
 /* Kill Register */
-#define NX_P7_CRB_KILL		NX_P7_SAT(0x1, 0x13)
 #define NX_P8_CRB_KILL		NX_P8_SAT(0x1, 0x13)
 #define NX_P9_CRB_KILL		NX_P9_SAT(0x1, 0x13)
 #define   NX_CRB_KILL_LPID_KILL		PPC_BIT(0)
@@ -211,62 +197,41 @@
 #define   NX_CRB_KILL_ALG_CH		PPC_BITMASK(56, 63)
 
 /* Fault Isolation Registers (FIR) */
-#define NX_P7_DE_FIR_DATA	NX_P7_SAT(0x4, 0x00)
 #define NX_P8_DE_FIR_DATA	NX_P8_SAT(0x4, 0x00)
 #define NX_P9_DE_FIR_DATA	NX_P9_SAT(0x4, 0x00)
-#define NX_P7_DE_FIR_DATA_CLR	NX_P7_SAT(0x4, 0x01)
 #define NX_P8_DE_FIR_DATA_CLR	NX_P8_SAT(0x4, 0x01)
 #define NX_P9_DE_FIR_DATA_CLR	NX_P9_SAT(0x4, 0x01)
-#define NX_P7_DE_FIR_DATA_SET	NX_P7_SAT(0x4, 0x02)
 #define NX_P8_DE_FIR_DATA_SET	NX_P8_SAT(0x4, 0x02)
 #define NX_P9_DE_FIR_DATA_SET	NX_P9_SAT(0x4, 0x02)
-#define NX_P7_DE_FIR_MASK	NX_P7_SAT(0x4, 0x06)
 #define NX_P8_DE_FIR_MASK	NX_P8_SAT(0x4, 0x03)
 #define NX_P9_DE_FIR_MASK	NX_P9_SAT(0x4, 0x03)
-#define NX_P7_DE_FIR_MASK_CLR	NX_P7_SAT(0x4, 0x07)
 #define NX_P8_DE_FIR_MASK_CLR	NX_P8_SAT(0x4, 0x04)
 #define NX_P9_DE_FIR_MASK_CLR	NX_P9_SAT(0x4, 0x04)
-#define NX_P7_DE_FIR_MASK_SET	NX_P7_SAT(0x4, 0x08)
 #define NX_P8_DE_FIR_MASK_SET	NX_P8_SAT(0x4, 0x05)
 #define NX_P9_DE_FIR_MASK_SET	NX_P9_SAT(0x4, 0x05)
-#define NX_P7_DE_FIR_ACTION0	NX_P7_SAT(0x4, 0x03)
 #define NX_P8_DE_FIR_ACTION0	NX_P8_SAT(0x4, 0x06)
 #define NX_P9_DE_FIR_ACTION0	NX_P9_SAT(0x4, 0x06)
-#define NX_P7_DE_FIR_ACTION1	NX_P7_SAT(0x4, 0x04)
 #define NX_P8_DE_FIR_ACTION1	NX_P8_SAT(0x4, 0x07)
 #define NX_P9_DE_FIR_ACTION1	NX_P9_SAT(0x4, 0x07)
-#define NX_P7_DE_FIR_WOF	NX_P7_SAT(0x4, 0x05)
 #define NX_P8_DE_FIR_WOF	NX_P8_SAT(0x4, 0x08)
-#define NX_P7_PB_FIR_DATA	NX_P7_SAT(0x2, 0x00)
 #define NX_P9_PB_FIR_DATA	NX_P9_SAT(0x2, 0x00)
 #define NX_P8_PB_FIR_DATA	NX_P8_SAT(0x2, 0x00)
-#define NX_P7_PB_FIR_DATA_CLR	NX_P7_SAT(0x2, 0x01)
 #define NX_P8_PB_FIR_DATA_CLR	NX_P8_SAT(0x2, 0x01)
 #define NX_P9_PB_FIR_DATA_CLR	NX_P9_SAT(0x2, 0x01)
-#define NX_P7_PB_FIR_DATA_SET	NX_P7_SAT(0x2, 0x02)
 #define NX_P8_PB_FIR_DATA_SET	NX_P8_SAT(0x2, 0x02)
 #define NX_P9_PB_FIR_DATA_SET	NX_P9_SAT(0x2, 0x02)
-#define NX_P7_PB_FIR_MASK	NX_P7_SAT(0x2, 0x06)
 #define NX_P8_PB_FIR_MASK	NX_P8_SAT(0x2, 0x03)
 #define NX_P9_PB_FIR_MASK	NX_P9_SAT(0x2, 0x03)
-#define NX_P7_PB_FIR_MASK_CLR	NX_P7_SAT(0x2, 0x07)
 #define NX_P8_PB_FIR_MASK_CLR	NX_P8_SAT(0x2, 0x04)
 #define NX_P9_PB_FIR_MASK_CLR	NX_P9_SAT(0x2, 0x04)
-#define NX_P7_PB_FIR_MASK_SET	NX_P7_SAT(0x2, 0x08)
 #define NX_P8_PB_FIR_MASK_SET	NX_P8_SAT(0x2, 0x05)
 #define NX_P9_PB_FIR_MASK_SET	NX_P9_SAT(0x2, 0x05)
-#define NX_P7_PB_FIR_ACTION0	NX_P7_SAT(0x2, 0x03)
 #define NX_P8_PB_FIR_ACTION0	NX_P8_SAT(0x2, 0x06)
 #define NX_P9_PB_FIR_ACTION0	NX_P9_SAT(0x2, 0x06)
-#define NX_P7_PB_FIR_ACTION1	NX_P7_SAT(0x2, 0x04)
 #define NX_P8_PB_FIR_ACTION1	NX_P8_SAT(0x2, 0x07)
 #define NX_P9_PB_FIR_ACTION1	NX_P9_SAT(0x2, 0x07)
-#define NX_P7_PB_FIR_WOF	NX_P7_SAT(0x2, 0x05)
 #define NX_P8_PB_FIR_WOF	NX_P8_SAT(0x2, 0x08)
-#define   NX_FIR_MCD_PB_CMD_HANG	PPC_BIT(0) /* P7 only */
 #define   NX_FIR_SHM_INV		PPC_BIT(1)
-#define   NX_FIR_MCD_ARRAY_ECC_CE	PPC_BIT(2) /* P7 only */
-#define   NX_FIR_MCD_ARRAY_ECC_UE	PPC_BIT(3) /* P7 only */
 #define   NX_FIR_CH0_ECC_CE		PPC_BIT(4)
 #define   NX_FIR_CH0_ECC_UE		PPC_BIT(5)
 #define   NX_FIR_CH1_ECC_CE		PPC_BIT(6)
@@ -296,9 +261,6 @@
 #define   NX_FIR_CRB_UE			PPC_BIT(31)
 #define   NX_FIR_CRB_SUE		PPC_BIT(32)
 #define   NX_FIR_DMA_RW_ECC_SUE		PPC_BIT(33)
-#define   NX_FIR_MCD_CFG_REG_PARITY	PPC_BIT(34) /* P7 only */
-#define   NX_FIR_MCD_RECOVERY_INV_STATE	PPC_BIT(35) /* P7 only */
-#define   NX_FIR_P7_PARITY		PPC_BIT(36) /* P7 only */
 #define   NX_FIR_CH4_ECC_CE		PPC_BIT(36) /* P8 only */
 #define   NX_FIR_CH5_ECC_UE_2		PPC_BIT(37) /* P8 only */
 #define   NX_FIR_P8_PARITY		PPC_BITMASK(48, 49)
@@ -312,14 +274,14 @@
 
 /* Arbitrary Coprocessor Type values */
 #define NX_CT_SYM	(1)
-#define NX_CT_ASYM	(2) /* on P7+ and P8 */
+#define NX_CT_ASYM	(2) /* on P8 */
 #define NX_CT_GZIP	(2) /* on P9 and later */
 #define NX_CT_842	(3)
 
 /* Coprocessor Instance counter
  * NX workbook, section 5.5.1
  * "Assigning <CT,CI> Values"
- * Only on P7+ and P8
+ * Only on P8
  */
 #define NX_SYM_CFG_CI_MAX	(511)
 #define NX_SYM_CFG_CI_LSHIFT	(2)
diff --git a/include/opal-api.h b/include/opal-api.h
index 2981b46..0b0ae19 100644
--- a/include/opal-api.h
+++ b/include/opal-api.h
@@ -788,55 +788,6 @@ enum {
 	OPAL_HMI_FLAGS_NEW_EVENT	= (1ull << 63), /* An event has been created */
 };
 
-enum {
-	OPAL_P7IOC_DIAG_TYPE_NONE	= 0,
-	OPAL_P7IOC_DIAG_TYPE_RGC	= 1,
-	OPAL_P7IOC_DIAG_TYPE_BI		= 2,
-	OPAL_P7IOC_DIAG_TYPE_CI		= 3,
-	OPAL_P7IOC_DIAG_TYPE_MISC	= 4,
-	OPAL_P7IOC_DIAG_TYPE_I2C	= 5,
-	OPAL_P7IOC_DIAG_TYPE_LAST	= 6
-};
-
-struct OpalIoP7IOCErrorData {
-	__be16 type;
-
-	/* GEM */
-	__be64 gemXfir;
-	__be64 gemRfir;
-	__be64 gemRirqfir;
-	__be64 gemMask;
-	__be64 gemRwof;
-
-	/* LEM */
-	__be64 lemFir;
-	__be64 lemErrMask;
-	__be64 lemAction0;
-	__be64 lemAction1;
-	__be64 lemWof;
-
-	union {
-		struct OpalIoP7IOCRgcErrorData {
-			__be64 rgcStatus;	/* 3E1C10 */
-			__be64 rgcLdcp;		/* 3E1C18 */
-		}rgc;
-		struct OpalIoP7IOCBiErrorData {
-			__be64 biLdcp0;		/* 3C0100, 3C0118 */
-			__be64 biLdcp1;		/* 3C0108, 3C0120 */
-			__be64 biLdcp2;		/* 3C0110, 3C0128 */
-			__be64 biFenceStatus;	/* 3C0130, 3C0130 */
-
-			uint8_t biDownbound;	/* BI Downbound or Upbound */
-		}bi;
-		struct OpalIoP7IOCCiErrorData {
-			__be64 ciPortStatus;	/* 3Dn008 */
-			__be64 ciPortLdcp;	/* 3Dn010 */
-
-			uint8_t ciPort;		/* Index of CI port: 0/1 */
-		}ci;
-	};
-};
-
 /**
  * This structure defines the overlay which will be used to store PHB error
  * data upon request.
@@ -846,13 +797,11 @@ enum {
 };
 
 enum {
-	OPAL_PHB_ERROR_DATA_TYPE_P7IOC = 1,
 	OPAL_PHB_ERROR_DATA_TYPE_PHB3 = 2,
 	OPAL_PHB_ERROR_DATA_TYPE_PHB4 = 3
 };
 
 enum {
-	OPAL_P7IOC_NUM_PEST_REGS = 128,
 	OPAL_PHB3_NUM_PEST_REGS = 256,
 	OPAL_PHB4_NUM_PEST_REGS = 512
 };
@@ -863,65 +812,6 @@ struct OpalIoPhbErrorCommon {
 	__be32 len;
 };
 
-struct OpalIoP7IOCPhbErrorData {
-	struct OpalIoPhbErrorCommon common;
-
-	__be32 brdgCtl;
-
-	// P7IOC utl regs
-	__be32 portStatusReg;
-	__be32 rootCmplxStatus;
-	__be32 busAgentStatus;
-
-	// P7IOC cfg regs
-	__be32 deviceStatus;
-	__be32 slotStatus;
-	__be32 linkStatus;
-	__be32 devCmdStatus;
-	__be32 devSecStatus;
-
-	// cfg AER regs
-	__be32 rootErrorStatus;
-	__be32 uncorrErrorStatus;
-	__be32 corrErrorStatus;
-	__be32 tlpHdr1;
-	__be32 tlpHdr2;
-	__be32 tlpHdr3;
-	__be32 tlpHdr4;
-	__be32 sourceId;
-
-	__be32 rsv3;
-
-	// Record data about the call to allocate a buffer.
-	__be64 errorClass;
-	__be64 correlator;
-
-	//P7IOC MMIO Error Regs
-	__be64 p7iocPlssr;                // n120
-	__be64 p7iocCsr;                  // n110
-	__be64 lemFir;                    // nC00
-	__be64 lemErrorMask;              // nC18
-	__be64 lemWOF;                    // nC40
-	__be64 phbErrorStatus;            // nC80
-	__be64 phbFirstErrorStatus;       // nC88
-	__be64 phbErrorLog0;              // nCC0
-	__be64 phbErrorLog1;              // nCC8
-	__be64 mmioErrorStatus;           // nD00
-	__be64 mmioFirstErrorStatus;      // nD08
-	__be64 mmioErrorLog0;             // nD40
-	__be64 mmioErrorLog1;             // nD48
-	__be64 dma0ErrorStatus;           // nD80
-	__be64 dma0FirstErrorStatus;      // nD88
-	__be64 dma0ErrorLog0;             // nDC0
-	__be64 dma0ErrorLog1;             // nDC8
-	__be64 dma1ErrorStatus;           // nE00
-	__be64 dma1FirstErrorStatus;      // nE08
-	__be64 dma1ErrorLog0;             // nE40
-	__be64 dma1ErrorLog1;             // nE48
-	__be64 pestA[OPAL_P7IOC_NUM_PEST_REGS];
-	__be64 pestB[OPAL_P7IOC_NUM_PEST_REGS];
-};
-
 struct OpalIoPhb3ErrorData {
 	struct OpalIoPhbErrorCommon common;
 
diff --git a/include/p7ioc-regs.h b/include/p7ioc-regs.h
deleted file mode 100644
index 4eb10d6..0000000
--- a/include/p7ioc-regs.h
+++ /dev/null
@@ -1,444 +0,0 @@
-/* Copyright 2013-2014 IBM Corp.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * 	http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
- * implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __P7IOC_REGS_H
-#define __P7IOC_REGS_H
-
-/*
- * Register definitions
- *
- * We only define some registers here. Ideally we should auto-generate
- * the full list from the spec. For now I add them as I need them
- */
-
-/* RGC GEM registers */
-#define P7IOC_GEM_XFIR		0x3E0008
-#define P7IOC_GEM_RFIR		0x3E0010
-#define P7IOC_GEM_RIRQFIR	0x3E0018
-#define P7IOC_GEM_MASK		0x3E0020
-#define P7IOC_GEM_RWOF		0x3E0028
-
-/* LEM register base */
-#define P7IOC_RGC_LEM_BASE		0x3E1E00
-#define P7IOC_BI_UP_LEM_BASE		0x3C0000
-#define P7IOC_BI_DOWN_LEM_BASE		0x3C0050
-#define P7IOC_CI_PORTn_LEM_BASE(n)	(0x3d0200 | ((n) * 0x1000))
-#define P7IOC_PHBn_LEM_BASE(n)		(0x000C00 | ((n) * 0x10000))
-#define P7IOC_MISC_LEM_BASE		0x3EA000
-#define P7IOC_I2C_LEM_BASE		0x3EB000
-
-/* LEM register offset */
-#define P7IOC_LEM_FIR_OFFSET		0x00
-#define P7IOC_LEM_FIR_AND_OFFSET	0x08
-#define P7IOC_LEM_FIR_OR_OFFSET		0x10
-#define P7IOC_LEM_ERR_MASK_OFFSET	0x18
-#define P7IOC_LEM_ERR_MASK_AND_OFFSET	0x20
-#define P7IOC_LEM_ERR_MASK_OR_OFFSET	0x28
-#define P7IOC_LEM_ACTION_0_OFFSET	0x30
-#define P7IOC_LEM_ACTION_1_OFFSET	0x38
-#define P7IOC_LEM_WOF_OFFSET		0x40
-
-/* HSS registers */
-#define P7IOC_HSS_BASE          0x3E8000
-#define P7IOC_HSS_STRIDE        0x200
-#define P7IOC_HSSn_CTL2_OFFSET  0x10
-#define P7IOC_HSSn_CTL3_OFFSET  0x18
-#define P7IOC_HSSn_CTL8_OFFSET  0x40
-#define P7IOC_HSSn_CTL9_OFFSET  0x48
-#define P7IOC_HSSn_CTL10_OFFSET 0x50
-#define P7IOC_HSSn_CTL11_OFFSET 0x58
-#define P7IOC_HSSn_CTL12_OFFSET 0x60
-#define P7IOC_HSSn_CTL13_OFFSET 0x68
-#define P7IOC_HSSn_CTL14_OFFSET 0x70
-#define P7IOC_HSSn_CTL15_OFFSET 0x78
-#define P7IOC_HSSn_CTL16_OFFSET 0x80
-#define P7IOC_HSSn_CTL17_OFFSET 0x88
-#define P7IOC_HSSn_CTL18_OFFSET 0x90
-#define P7IOC_HSSn_CTL19_OFFSET 0x98
-#define P7IOC_HSSn_CTL20_OFFSET 0xa0
-#define P7IOC_HSSn_CTL21_OFFSET 0xa8
-#define P7IOC_HSSn_CTL22_OFFSET 0xb0
-#define P7IOC_HSSn_CTL23_OFFSET 0xb8
-
-/* CI Routing registers & helper macros */
-#define P7IOC_CI_RMATC_REG(i)		(0x3D0400ul + ((i) << 4))
-#define P7IOC_CI_RMASK_REG(i)		(0x3D0408ul + ((i) << 4))
-
-#define P7IOC_CI_RMATC_PORT(n)		PPC_BIT(n)
-#define P7IOC_CI_RMATC_ADDR_VALID	PPC_BIT(16)
-#define P7IOC_CI_RMATC_BUID_VALID	PPC_BIT(17)
-#define P7IOC_CI_RMATC_TYPE_VALID	PPC_BIT(18)
-
-/* AIB Addresses are 48-bit, the top 32 are used in
- * the routing tables, we thus shift by 16
- */
-#define P7IOC_CI_RMATC_ENCODE_ADDR(addr)	((uint32_t)((addr) >> 16))
-#define P7IOC_CI_RMATC_ENCODE_BUID(buid)	((uint32_t)((buid) << 20))
-#define P7IOC_CI_RMATC_ENCODE_TYPE(type)	((uint32_t)(type))
-
-/* CI port numbers */
-#define P7IOC_CI_PHB_PORT(pnum)		((pnum) + 2)
-#define P7IOC_CI_UPSTREAM_PORT		0
-#define P7IOC_CI_RGC_PORT		1
-
-/* Other random chip registers */
-#define P7IOC_CHIP_FENCE_SHADOW		0x3ec010
-#define P7IOC_CHIP_FENCE_WOF		0x3ec018
-#define P7IOC_CCRR			0x3e1c00
-
-/* CI registers */
-#define P7IOC_CIn_BASE(n)		(0x3d0000 | ((n) * 0x1000))
-#define P7IOC_CIn_LEM_FIR(n)		(P7IOC_CIn_BASE(n) + 0x200)
-#define P7IOC_CIn_LEM_FIR_AND(n)	(P7IOC_CIn_BASE(n) + 0x208)
-#define P7IOC_CIn_LEM_FIR_OR(n)		(P7IOC_CIn_BASE(n) + 0x210)
-#define P7IOC_CIn_LEM_ERR_MASK(n)	(P7IOC_CIn_BASE(n) + 0x218)
-#define P7IOC_CIn_LEM_ERR_MASK_AND(n)	(P7IOC_CIn_BASE(n) + 0x220)
-#define P7IOC_CIn_LEM_ERR_MASK_OR(n)	(P7IOC_CIn_BASE(n) + 0x228)
-
-/*
- * PHB registers
- */
-
-/* PHB Fundamental register set A */
-#define PHB_BUID			0x100
-#define   PHB_BUID_LSI			PPC_BITMASK(7,15)
-#define   PHB_BUID_MSI			PPC_BITMASK(23,31)
-#define PHB_DMA_CHAN_STATUS		0x110
-#define PHB_CPU_LOADSTORE_STATUS	0x120
-#define PHB_CONFIG_DATA			0x130
-#define PHB_LOCK0			0x138
-#define PHB_CONFIG_ADDRESS		0x140
-#define   PHB_CA_ENABLE			PPC_BIT(0)
-#define	  PHB_CA_BUS			PPC_BITMASK(4,11)
-#define   PHB_CA_DEV			PPC_BITMASK(12,16)
-#define   PHB_CA_FUNC			PPC_BITMASK(17,19)
-#define   PHB_CA_BDFN			PPC_BITMASK(4,19) /* bus,dev,func */
-#define   PHB_CA_REG			PPC_BITMASK(20,31)
-#define PHB_LOCK1			0x148
-#define PHB_PHB2_CONFIG			0x160
-#define   PHB_PHB2C_64B_TCE_EN		PPC_BIT(2)
-#define   PHB_PHB2C_32BIT_MSI_EN	PPC_BIT(8)
-#define   PHB_PHB2C_IO_EN		PPC_BIT(12)
-#define   PHB_PHB2C_64BIT_MSI_EN	PPC_BIT(14)
-#define   PHB_PHB2C_M32_EN		PPC_BIT(16)
-#define PHB_IO_BASE_ADDR		0x170
-#define PHB_IO_BASE_MASK		0x178
-#define PHB_IO_START_ADDR		0x180
-#define PHB_M32_BASE_ADDR		0x190
-#define PHB_M32_BASE_MASK		0x198
-#define PHB_M32_START_ADDR		0x1a0
-#define PHB_M64_UPPER_BITS		0x1f0
-#define PHB_TCE_KILL			0x210
-#define   PHB_TCEKILL_PAIR		PPC_BIT(0)
-#define   PHB_TCEKILL_ADDR		PPC_BITMASK(16,59)
-#define PHB_TCE_PREFETCH		0x218
-#define PHB_IODA_ADDR			0x220
-#define   PHB_IODA_AD_AUTOINC		PPC_BIT(0)
-#define	  PHB_IODA_AD_TSEL		PPC_BITMASK(11,15)
-#define	  PHB_IODA_AD_TADR		PPC_BITMASK(48,63)
-#define PHB_IODA_DATA0			0x228
-#define PHB_IODA_DATA1			0x230
-#define PHB_LOCK2			0x240
-#define PHB_XIVE_UPDATE			0x248
-#define PHB_PHB2_GEN_CAP		0x250
-#define PHB_PHB2_TCE_CAP		0x258
-#define PHB_PHB2_IRQ_CAP		0x260
-#define PHB_PHB2_EEH_CAP		0x268
-#define PHB_PAPR_ERR_INJ_CTL		0x2b0
-#define   PHB_PAPR_ERR_INJ_CTL_INB	PPC_BIT(0)
-#define   PHB_PAPR_ERR_INJ_CTL_OUTB	PPC_BIT(1)
-#define   PHB_PAPR_ERR_INJ_CTL_STICKY	PPC_BIT(2)
-#define   PHB_PAPR_ERR_INJ_CTL_CFG	PPC_BIT(3)
-#define   PHB_PAPR_ERR_INJ_CTL_RD	PPC_BIT(4)
-#define   PHB_PAPR_ERR_INJ_CTL_WR	PPC_BIT(5)
-#define   PHB_PAPR_ERR_INJ_CTL_FREEZE	PPC_BIT(6)
-#define PHB_PAPR_ERR_INJ_ADDR		0x2b8
-#define PHB_PAPR_ERR_INJ_MASK		0x2c0
-#define   PHB_PAPR_ERR_INJ_MASK_CFG		PPC_BITMASK(4,11)
-#define   PHB_PAPR_ERR_INJ_MASK_MMIO		PPC_BITMASK(16,39)	/* 16M aligned */
-#define   PHB_PAPR_ERR_INJ_MASK_IO		PPC_BITMASK(16,47)	/* 64K aligned */
-#define   PHB_PAPR_ERR_INJ_MASK_DMA		PPC_BITMASK(60,63)	/* 16 window */
-#define PHB_ETU_ERR_SUMMARY		0x2c8
-
-/*  UTL registers */
-#define UTL_SYS_BUS_CONTROL		0x400
-#define UTL_STATUS			0x408
-#define UTL_SYS_BUS_AGENT_STATUS	0x410
-#define UTL_SYS_BUS_AGENT_ERR_SEVERITY	0x418
-#define UTL_SYS_BUS_AGENT_IRQ_EN	0x420
-#define UTL_SYS_BUS_BURST_SZ_CONF	0x440
-#define UTL_REVISION_ID			0x448
-#define UTL_OUT_POST_HDR_BUF_ALLOC	0x4c0
-#define UTL_OUT_POST_DAT_BUF_ALLOC	0x4d0
-#define UTL_IN_POST_HDR_BUF_ALLOC	0x4e0
-#define UTL_IN_POST_DAT_BUF_ALLOC	0x4f0
-#define UTL_OUT_NP_BUF_ALLOC		0x500
-#define UTL_IN_NP_BUF_ALLOC		0x510
-#define UTL_PCIE_TAGS_ALLOC		0x520
-#define UTL_GBIF_READ_TAGS_ALLOC	0x530
-#define UTL_PCIE_PORT_CONTROL		0x540
-#define UTL_PCIE_PORT_STATUS		0x548
-#define UTL_PCIE_PORT_ERROR_SEV		0x550
-#define UTL_PCIE_PORT_IRQ_EN		0x558
-#define UTL_RC_STATUS			0x560
-#define UTL_RC_ERR_SEVERITY		0x568
-#define UTL_RC_IRQ_EN			0x570
-#define UTL_EP_STATUS			0x578
-#define UTL_EP_ERR_SEVERITY		0x580
-#define UTL_EP_ERR_IRQ_EN		0x588
-#define UTL_PCI_PM_CTRL1		0x590
-#define UTL_PCI_PM_CTRL2		0x598
-#define UTL_GP_CTL1			0x5a0
-#define UTL_GP_CTL2			0x5a8
-
-/* PCI-E Stack registers */
-#define PHB_PCIE_SYSTEM_CONFIG		0x600
-#define PHB_PCIE_BUS_NUMBER		0x608
-#define PHB_PCIE_SYSTEM_TEST		0x618
-#define PHB_PCIE_LINK_MANAGEMENT	0x630
-#define PHB_PCIE_DLP_TRAIN_CTL		0x640
-#define   PHB_PCIE_DLP_TCTX_DISABLE	PPC_BIT(1)
-#define   PHB_PCIE_DLP_TCRX_DISABLED	PPC_BIT(16)
-#define   PHB_PCIE_DLP_TC_DL_LINKUP	PPC_BIT(21)
-#define   PHB_PCIE_DLP_TC_DL_PGRESET	PPC_BIT(22)
-#define   PHB_PCIE_DLP_TC_DL_LINKACT	PPC_BIT(23)
-#define PHB_PCIE_SLOP_LOOPBACK_STATUS	0x648
-#define PHB_PCIE_AER_CONTROL		0x650
-#define PHB_PCIE_AUX_POWER_CONTROL	0x658
-#define PHB_PCIE_SLOTCTL1		0x660
-#define PHB_PCIE_SLOTCTL2		0x668
-#define   PHB_PCIE_SLOTCTL2_SLOTWAKE	PPC_BIT(16)
-#define   PHB_PCIE_SLOTCTL2_PWR_EN_STAT	PPC_BIT(17)
-#define   PHB_PCIE_SLOTCTL2_RCK_EN_STAT	PPC_BIT(18)
-#define   PHB_PCIE_SLOTCTL2_PERST_STAT	PPC_BIT(19)
-#define   PHB_PCIE_SLOTCTL2_PLED_S	PPC_BITMASK(20,21) /* use PCIE_INDIC_* */
-#define   PHB_PCIE_SLOTCTL2_ALED_S	PPC_BITMASK(22,23)
-#define   PHB_PCIE_SLOTCTL2_PRSTN_STAT	PPC_BIT(24)
-#define   PHB_PCIE_SLOTCTL2_PWRFLT_STAT	PPC_BIT(25)
-#define PHB_PCIE_UTL_CONFIG		0x670
-#define PHB_PCIE_DLP_CONTROL		0x678
-#define PHB_PCIE_UTL_ERRLOG1		0x680
-#define PHB_PCIE_UTL_ERRLOG2		0x688
-#define PHB_PCIE_UTL_ERRLOG3		0x690
-#define PHB_PCIE_UTL_ERRLOG4		0x698
-#define PHB_PCIE_DLP_ERRLOG1		0x6a0
-#define PHB_PCIE_DLP_ERRLOG2		0x6a8
-#define PHB_PCIE_UTL_ERR_INJECT		0x6c0
-#define PHB_PCIE_TLDLP_ERR_INJECT	0x6c8
-#define PHB_PCIE_STRAPPING		0x700
-
-/* Fundamental register set B */
-#define PHB_VERSION			0x800
-#define PHB_RESET			0x808
-#define PHB_CONTROL			0x810
-#define PHB_AIB_RX_CRED_INIT_TIMER	0x818
-#define PHB_AIB_RX_CMD_CRED		0x820
-#define PHB_AIB_RX_DATA_CRED		0x828
-#define PHB_AIB_TX_CMD_CRED		0x830
-#define PHB_AIB_TX_DATA_CRED		0x838
-#define PHB_AIB_TX_CHAN_MAPPING		0x840
-#define PHB_AIB_TX_CRED_SYNC_CTRL	0x848
-#define PHB_LEGACY_CTRL			0x850
-#define PHB_AIB_TAG_ENABLE		0x858
-#define PHB_AIB_FENCE_CTRL		0x860
-#define PHB_TCE_TAG_ENABLE		0x868
-#define PHB_TCE_WATERMARK		0x870
-#define PHB_TIMEOUT_CTRL1		0x878
-#define PHB_TIMEOUT_CTRL2		0x880
-#define PHB_QUIESCE_DMA_G		0x888
-#define PHB_AIB_TAG_STATUS		0x900
-#define PHB_TCE_TAG_STATUS		0x908
-
-/* FIR & Error registers */
-#define PHB_LEM_FIR_ACCUM		0xc00
-#define PHB_LEM_FIR_AND_MASK		0xc08
-#define PHB_LEM_FIR_OR_MASK		0xc10
-#define PHB_LEM_ERROR_MASK		0xc18
-#define PHB_LEM_ERROR_AND_MASK		0xc20
-#define PHB_LEM_ERROR_OR_MASK		0xc28
-#define PHB_LEM_ACTION0			0xc30
-#define PHB_LEM_ACTION1			0xc38
-#define PHB_LEM_WOF			0xc40
-#define PHB_ERR_STATUS			0xc80
-#define PHB_ERR1_STATUS			0xc88
-#define PHB_ERR_INJECT			0xc90
-#define PHB_ERR_LEM_ENABLE		0xc98
-#define PHB_ERR_IRQ_ENABLE		0xca0
-#define PHB_ERR_FREEZE_ENABLE		0xca8
-#define PHB_ERR_AIB_FENCE_ENABLE	0xcb0
-#define PHB_ERR_LOG_0			0xcc0
-#define PHB_ERR_LOG_1			0xcc8
-#define PHB_ERR_STATUS_MASK		0xcd0
-#define PHB_ERR1_STATUS_MASK		0xcd8
-
-#define PHB_OUT_ERR_STATUS		0xd00
-#define PHB_OUT_ERR1_STATUS		0xd08
-#define PHB_OUT_ERR_INJECT		0xd10
-#define PHB_OUT_ERR_LEM_ENABLE		0xd18
-#define PHB_OUT_ERR_IRQ_ENABLE		0xd20
-#define PHB_OUT_ERR_FREEZE_ENABLE	0xd28
-#define PHB_OUT_ERR_AIB_FENCE_ENABLE	0xd30
-#define PHB_OUT_ERR_LOG_0		0xd40
-#define PHB_OUT_ERR_LOG_1		0xd48
-#define PHB_OUT_ERR_STATUS_MASK		0xd50
-#define PHB_OUT_ERR1_STATUS_MASK	0xd58
-
-#define PHB_INA_ERR_STATUS		0xd80
-#define PHB_INA_ERR1_STATUS		0xd88
-#define PHB_INA_ERR_INJECT		0xd90
-#define PHB_INA_ERR_LEM_ENABLE		0xd98
-#define PHB_INA_ERR_IRQ_ENABLE		0xda0
-#define PHB_INA_ERR_FREEZE_ENABLE	0xda8
-#define PHB_INA_ERR_AIB_FENCE_ENABLE	0xdb0
-#define PHB_INA_ERR_LOG_0		0xdc0
-#define PHB_INA_ERR_LOG_1		0xdc8
-#define PHB_INA_ERR_STATUS_MASK		0xdd0
-#define PHB_INA_ERR1_STATUS_MASK	0xdd8
-
-#define PHB_INB_ERR_STATUS		0xe00
-#define PHB_INB_ERR1_STATUS		0xe08
-#define PHB_INB_ERR_INJECT		0xe10
-#define PHB_INB_ERR_LEM_ENABLE		0xe18
-#define PHB_INB_ERR_IRQ_ENABLE		0xe20
-#define PHB_INB_ERR_FREEZE_ENABLE	0xe28
-#define PHB_INB_ERR_AIB_FENCE_ENABLE	0xe30
-#define PHB_INB_ERR_LOG_0		0xe40
-#define PHB_INB_ERR_LOG_1		0xe48
-#define PHB_INB_ERR_STATUS_MASK		0xe50
-#define PHB_INB_ERR1_STATUS_MASK	0xe58
-
-/* Performance monitor & Debug registers */
-#define PHB_TRACE_CONTROL		0xf80
-#define PHB_PERFMON_CONFIG		0xf88
-#define PHB_PERFMON_CTR0		0xf90
-#define PHB_PERFMON_CTR1		0xf98
-#define PHB_PERFMON_CTR2		0xfa0
-#define PHB_PERFMON_CTR3		0xfa8
-#define PHB_HOTPLUG_OVERRIDE		0xfb0
-
-/*
- * IODA tables
- */
-
-#define IODA_TBL_HRT		0
-#define IODA_TBL_LIST		1
-#define IODA_TBL_LXIVT		2
-#define IODA_TBL_MIST		3
-#define IODA_TBL_MXIVT		4
-#define IODA_TBL_MVT		5
-#define IODA_TBL_PELTM		6
-#define IODA_TBL_PESTA		7
-#define IODA_TBL_PESTB		8
-#define IODA_TBL_TVT		9
-#define IODA_TBL_TCAM		10
-#define IODA_TBL_TDR		11
-#define IODA_TBL_PELTV		12
-#define IODA_TBL_M64BT		16
-#define IODA_TBL_IODT		17
-#define IODA_TBL_M32DT		18
-#define IODA_TBL_M64DT		19
-#define IODA_TBL_PEEV		20
-
-/* L/M XIVT */
-#define IODA_XIVT_SERVER		PPC_BITMASK(8,23)
-#define IODA_XIVT_PRIORITY		PPC_BITMASK(24,31)
-#define IODA_XIVT_PENUM			PPC_BITMASK(41,47)
-#define IODA_XIVT_HUBNUM		PPC_BITMASK(58,59)
-
-/* M64BT */
-#define IODA_M64BT_ENABLE		PPC_BIT(0)
-#define IODA_M64BT_BASE			PPC_BITMASK(8,31)
-#define IODA_M64BT_MASK			PPC_BITMASK(40,63)
-
-/* IODT/M32DT/M64DX */
-#define IODA_XXDT_PE			PPC_BITMASK(0,6)
-
-/* PELTM */
-#define IODA_PELTM_BUS			PPC_BITMASK(0,7)
-#define IODA_PELTM_DEV			PPC_BITMASK(8,12)
-#define IODA_PELTM_FUNC			PPC_BITMASK(13,15)
-#define IODA_PELTM_BUS_VALID		PPC_BITMASK(16,18)
-#define  IODA_BUS_VALID_ANY		0
-#define  IODA_BUS_VALID_3_BITS		2
-#define  IODA_BUS_VALID_4_BITS		3
-#define  IODA_BUS_VALID_5_BITS		4
-#define  IODA_BUS_VALID_6_BITS		5
-#define  IODA_BUS_VALID_7_BITS		6
-#define  IODA_BUS_VALID_ALL		7
-#define IODA_PELTM_DEV_VALID		PPC_BIT(19)
-#define IODA_PELTM_FUNC_VALID		PPC_BIT(20)
-
-/* TVT */
-#define IODA_TVT0_TABLE_ADDR		PPC_BITMASK(0,47)
-#define IODA_TVT0_BUS_VALID		PPC_BITMASK(48,50)
-#define IODA_TVT0_TCE_TABLE_SIZE	PPC_BITMASK(51,55)
-#define IODA_TVT0_BUS_NUM		PPC_BITMASK(56,63)
-#define IODA_TVT1_DEV_VALID		PPC_BIT(2)
-#define IODA_TVT1_DEV_NUM		PPC_BITMASK(3,7)
-#define IODA_TVT1_HUB_NUM		PPC_BITMASK(10,11)
-#define IODA_TVT1_FUNC_VALID		PPC_BIT(12)
-#define IODA_TVT1_FUNC_NUM		PPC_BITMASK(13,15)
-#define IODA_TVT1_IO_PSIZE		PPC_BITMASK(19,23)
-#define IODA_TVT1_PE_NUM		PPC_BITMASK(57,63)
-
-/* MVT */
-#define IODA_MVT_VALID			PPC_BIT(0)
-#define IODA_MVT_BUS_VALID		PPC_BITMASK(21,23)
-#define IODA_MVT_BUS_NUM		PPC_BITMASK(24,31)
-#define IODA_MVT_PE_NUM			PPC_BITMASK(41,47)
-#define IODA_MVT_DEV_VALID		PPC_BIT(50)
-#define IODA_MVT_DEV_NUM		PPC_BITMASK(51,55)
-#define IODA_MVT_FUNC_VALID		PPC_BIT(60)
-#define IODA_MVT_FUNC_NUM		PPC_BITMASK(61,63)
-
-/* PESTA */
-#define IODA_PESTA_MMIO_FROZEN		PPC_BIT(0)
-#define IODA_PESTA_MMIO_CAUSE		PPC_BIT(2)
-#define IODA_PESTA_CFG_READ		PPC_BIT(3)
-#define IODA_PESTA_CFG_WRITE		PPC_BIT(4)
-#define IODA_PESTA_TTYPE		PPC_BITMASK(5,7)
-#define   PESTA_TTYPE_DMA_WRITE		0
-#define   PESTA_TTYPE_MSI		1
-#define   PESTA_TTYPE_DMA_READ		2
-#define   PESTA_TTYPE_DMA_READ_RESP	3
-#define   PESTA_TTYPE_MMIO_LOAD		4
-#define   PESTA_TTYPE_MMIO_STORE	5
-#define   PESTA_TTYPE_OTHER		7
-#define IODA_PESTA_CA_RETURN		PPC_BIT(8)
-#define IODA_PESTA_UTL_RTOS_TIMEOUT	PPC_BIT(8) /* Same bit as CA return */
-#define IODA_PESTA_UR_RETURN		PPC_BIT(9)
-#define IODA_PESTA_UTL_NONFATAL		PPC_BIT(10)
-#define IODA_PESTA_UTL_FATAL		PPC_BIT(11)
-#define IODA_PESTA_TAG_REUSE_ERROR	PPC_BIT(12)
-#define IODA_PESTA_PARITY_UE		PPC_BIT(13)
-#define IODA_PESTA_UTL_CORRECTABLE	PPC_BIT(14)
-#define IODA_PESTA_UTL_INTERRUPT	PPC_BIT(15)
-#define IODA_PESTA_MMIO_XLATE		PPC_BIT(16)
-#define IODA_PESTA_IODA_ERROR		PPC_BIT(16) /* Same bit as MMIO xlate */
-#define IODA_PESTA_TVT_EXT_ERROR	PPC_BIT(17)
-#define IODA_PESTA_TCE_PAGE_FAULT	PPC_BIT(18)
-#define IODA_PESTA_TCE_ACCESS_FAULT	PPC_BIT(19)
-#define IODA_PESTA_DMA_RESP_TIMEOUT	PPC_BIT(20)
-#define IODA_PESTA_AIB_SIZE_INVALID	PPC_BIT(21)
-#define IODA_PESTA_LEM_BIT		PPC_BITMASK(26,31)
-#define IODA_PESTA_RID			PPC_BITMASK(32,47)
-#define IODA_PESTA_MSI_DATA		PPC_BITMASK(48,63)
-
-/* PESTB */
-#define IODA_PESTB_DMA_STOPPED		PPC_BIT(0)
-#define IODA_PESTB_FAIL_ADDR		PPC_BITMASK(3,63)
-
-#endif /* __P7IOC_REGS_H */
diff --git a/include/p7ioc.h b/include/p7ioc.h
deleted file mode 100644
index 96f9209..0000000
--- a/include/p7ioc.h
+++ /dev/null
@@ -1,367 +0,0 @@
-/* Copyright 2013-2014 IBM Corp.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * 	http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
- * implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __P7IOC_H
-#define __P7IOC_H
-
-#include <cec.h>
-#include <pci.h>
-
-#include <ccan/container_of/container_of.h>
-
-/*
- * Memory windows and BUID assignment
- *
- * - GX BAR assignment
- *
- *   I don't know of any spec here, so we're going to mimmic what
- *   OPAL seems to be doing:
- *
- *     - BAR 0 :   32M, disabled. We just leave it alone.
- *     - BAR 1 :    8G, enabled. Appears to correspond to the MMIO
- *                      space of the IOC itself and the PCI IO space
- *     - BAR 2:   128G,
- *     - BAR 3:   128G,
- *     - BAR 4:   128G, all 3 contiguous, forming a single 368G region
- *                      and is used for M32 and M64 PHB windows.
- *
- * - Memory map
- *
- *    MWIN1 = BAR1 (8G)
- *    MWIN2 = BAR2,3,4 (384G)
- *
- *    MWIN2 is divided into 6 * 4G regions for use by M32's (*) and
- *    6 * 32G regions for use by M64's.
- *
- * (*) The M32 will typically be configured to only 2G or so, however
- *     the OS is in control of that setting, and since we have to reserve
- *     a power of two, we reserve the whole 4G.
- *
- *    - RGC registers: MWIN1 + 0x00000000
- *    - PHBn IO space: MWIN1 + 0x01000000 + n * 0x00800000 (8M each)
- *    - PHBn M32     : MWIN2 + n * 0x1_00000000 (4G each)
- *    - PHBn M64     : MWIN2 + (n + 1) * 0x8_00000000 (32G each)
- *
- * - BUID map. The RGC has interrupts, each PHB has then its own
- *             interrupts (errors etc...), 4 LSIs and 256 LSIs so
- *             respectively 1 BUID for self, 1 for LSIs and 16 for LSIs
- *
- *   We keep all BUIDs below 0x10 reserved. They will be used for things
- *   like the PSI controller, the NX unit, etc.. in the P7 chip.
- *
- *    RGC	: 0x010
- *    PHBn LSI	: 0x040 + n * 0x40 (   1 BUID)
- *    PHBn MSI  : 0x060 + n * 0x40 (0x10 BUIDs)
- *
- * -> For routing, each PHB gets a block of 0x40 BUIDs:
- *
- *	from 0x40 * (n + 1) to 0x7f * (n + 1)
- */
-
-/* Some definitions resulting from the above description
- *
- * Note: A better approach might be to read the GX BAR content
- *       and isolate the biggest contiguous windows. From there
- *       we could divide things algorithmically and thus be
- *       less sensitive to a change in the memory map by the FSP
- */
-#define MWIN1_SIZE	0x200000000ul	/* MWIN1 is 8G */
-#define MWIN2_SIZE     0x6000000000ul	/* MWIN2 is 384G */
-#define PHB_IO_OFFSET	 0x01000000ul	/* Offset of PHB IO space in MWIN1 */
-#define PHB_IO_SIZE	 0x00800000ul
-#define PHB_M32_OFFSET	        0x0ul	/* Offset of PHB M32 space in MWIN2 */
-#define PHB_M32_SIZE	0x100000000ul
-#define PHB_M64_OFFSET	0x800000000ul	/* Offset of PHB M64 space in MWIN2 */
-#define PHB_M64_SIZE	0x800000000ul
-#define RGC_BUID_OFFSET		0x10	/* Offset of RGC BUID */
-#define PHB_BUID_OFFSET		0x40	/* Offset of PHB BUID blocks */
-#define PHB_BUID_SIZE		0x40	/* Size of PHB BUID blocks */
-#define PHB_BUID_LSI_OFFSET	0x00	/* Offset of LSI in PHB BUID block */
-#define PHB_BUID_MSI_OFFSET	0x20	/* Offset of MSI in PHB BUID block */
-#define PHB_BUID_MSI_SIZE	0x10	/* Size of PHB MSI BUID block */
-
-#define PHBn_IO_BASE(n)		(PHB_IO_OFFSET + (n) * PHB_IO_SIZE)
-#define PHBn_M32_BASE(n)	(PHB_M32_OFFSET + (n) * PHB_M32_SIZE)
-#define PHBn_M64_BASE(n)	(PHB_M64_OFFSET + (n) * PHB_M64_SIZE)
-#define PHBn_BUID_BASE(n)	(PHB_BUID_OFFSET + (n) * PHB_BUID_SIZE)
-
-#define BUID_TO_PHB(buid)	(((buid) - PHB_BUID_OFFSET) / PHB_BUID_SIZE)
-
-/* p7ioc has 6 PHBs */
-#define P7IOC_NUM_PHBS		6
-
-/* M32 window setting at boot:
- *
- * To allow for DMA, we need to split the 32-bit PCI address space between
- * MMIO and DMA. For now, we use a 2G/2G split with MMIO at the top.
- *
- * Note: The top 64K of the M32 space are used by MSIs. This is not
- * visible here but need to be conveyed to the OS one way or another
- *
- * Note2: The space reserved in the system address space for M32 is always
- * 4G. That we chose to use a smaller portion of it is not relevant to
- * the upper levels. To keep things consistent, the offset we apply to
- * the window start is also applied on the host side.
- */
-#define M32_PCI_START	0x80000000
-#define M32_PCI_SIZE	0x80000000
-
-/* PHB registers exist in both a hard coded space and a programmable
- * AIB space. We program the latter to the values recommended in the
- * documentation:
- *
- *	0x80000 + n * 0x10000
- */
-#define PHBn_ASB_BASE(n)	(((n) << 16))
-#define PHBn_ASB_SIZE		0x10000ul
-#define PHBn_AIB_BASE(n)	(0x80000ul + ((n) << 16))
-#define PHBn_AIB_SIZE		0x10000ul
-
-/*
- * LSI interrupts
- *
- * The LSI interrupt block supports 8 interrupts. 4 of them are the
- * standard PCIe INTA..INTB. The rest is for additional functions
- * of the PHB
- */
-#define PHB_LSI_PCIE_INTA		0
-#define PHB_LSI_PCIE_INTB		1
-#define PHB_LSI_PCIE_INTC		2
-#define PHB_LSI_PCIE_INTD		3
-#define PHB_LSI_PCIE_HOTPLUG		4
-#define PHB_LSI_PCIE_PERFCTR		5
-#define PHB_LSI_PCIE_UNUSED		6
-#define PHB_LSI_PCIE_ERROR		7
-
-/* P7IOC PHB slot states */
-#define P7IOC_SLOT_NORMAL		PCI_SLOT_STATE_NORMAL
-#define P7IOC_SLOT_LINK			PCI_SLOT_STATE_LINK
-#define   P7IOC_SLOT_LINK_START		(P7IOC_SLOT_LINK + 1)
-#define   P7IOC_SLOT_LINK_WAIT		(P7IOC_SLOT_LINK + 2)
-#define P7IOC_SLOT_HRESET		PCI_SLOT_STATE_HRESET
-#define   P7IOC_SLOT_HRESET_START	(P7IOC_SLOT_HRESET + 1)
-#define   P7IOC_SLOT_HRESET_TRAINING	(P7IOC_SLOT_HRESET + 2)
-#define   P7IOC_SLOT_HRESET_DELAY	(P7IOC_SLOT_HRESET + 3)
-#define   P7IOC_SLOT_HRESET_DELAY2	(P7IOC_SLOT_HRESET + 4)
-#define P7IOC_SLOT_FRESET		PCI_SLOT_STATE_FRESET
-#define   P7IOC_SLOT_FRESET_START	(P7IOC_SLOT_FRESET + 1)
-#define   P7IOC_SLOT_FRESET_TRAINING	(P7IOC_SLOT_FRESET + 2)
-#define   P7IOC_SLOT_FRESET_POWER_OFF	(P7IOC_SLOT_FRESET + 3)
-#define   P7IOC_SLOT_FRESET_POWER_ON	(P7IOC_SLOT_FRESET + 4)
-#define   P7IOC_SLOT_FRESET_ASSERT	(P7IOC_SLOT_FRESET + 5)
-#define   P7IOC_SLOT_FRESET_DEASSERT	(P7IOC_SLOT_FRESET + 6)
-#define P7IOC_SLOT_CRESET		PCI_SLOT_STATE_CRESET
-#define   P7IOC_SLOT_CRESET_START	(P7IOC_SLOT_CRESET + 1)
-
-/*
- * In order to support error detection and recovery on different
- * types of IOCs (e.g. P5IOC, P7IOC, P8IOC), the best bet would
- * be make the implementation to be 2 layers: OPAL layer and IOC
- * layer. The OPAL layer just handles the general information and
- * IOC layer should process much more detailed information, which
- * is sensitive to itself.
- */
-#define P7IOC_ERR_SRC_NONE	0
-#define P7IOC_ERR_SRC_EI	1
-#define P7IOC_ERR_SRC_RGC	2
-#define P7IOC_ERR_SRC_BI_UP	3
-#define P7IOC_ERR_SRC_BI_DOWN	4
-#define P7IOC_ERR_SRC_CI_P0	5
-#define P7IOC_ERR_SRC_CI_P1	6
-#define P7IOC_ERR_SRC_CI_P2	7
-#define P7IOC_ERR_SRC_CI_P3	8
-#define P7IOC_ERR_SRC_CI_P4	9
-#define P7IOC_ERR_SRC_CI_P5	10
-#define P7IOC_ERR_SRC_CI_P6	11
-#define P7IOC_ERR_SRC_CI_P7	12
-#define P7IOC_ERR_SRC_PHB0	13
-#define P7IOC_ERR_SRC_PHB1	14
-#define P7IOC_ERR_SRC_PHB2	15
-#define P7IOC_ERR_SRC_PHB3	16
-#define P7IOC_ERR_SRC_PHB4	17
-#define P7IOC_ERR_SRC_PHB5	18
-#define P7IOC_ERR_SRC_MISC	19
-#define P7IOC_ERR_SRC_I2C	20
-#define P7IOC_ERR_SRC_LAST	21
-
-#define P7IOC_ERR_CLASS_NONE	0
-#define P7IOC_ERR_CLASS_GXE	1
-#define P7IOC_ERR_CLASS_PLL	2
-#define P7IOC_ERR_CLASS_RGA	3
-#define P7IOC_ERR_CLASS_PHB	4
-#define P7IOC_ERR_CLASS_ER	5
-#define P7IOC_ERR_CLASS_INF	6
-#define P7IOC_ERR_CLASS_MAL	7
-#define P7IOC_ERR_CLASS_LAST	8
-
-/*
- * P7IOC error descriptor. For errors from PHB and PE, they
- * will be cached to the corresponding PHBs. However, the
- * left errors (e.g. EI, CI Port0/1) will be cached to the
- * IOC directly.
- */
-struct p7ioc_err {
-	uint32_t err_src;
-	uint32_t err_class;
-	uint32_t err_bit;
-};
-
-struct p7ioc;
-
-#define P7IOC_PHB_CFG_USE_ASB	0x00000001 /* ASB to access PCI-CFG     */
-#define P7IOC_PHB_CFG_BLOCKED	0x00000002 /* PCI-CFG blocked except 0	*/
-
-struct p7ioc_phb {
-	uint8_t				index;	/* 0..5 index inside p7ioc */
-	uint8_t				gen;
-	uint32_t			flags;
-	bool				broken;
-#define P7IOC_REV_DD10	0x00a20001
-#define P7IOC_REV_DD11	0x00a20002
-	uint32_t			rev;	/* Both major and minor have 2 bytes */
-	void				*regs_asb;
-	void				*regs;	/* AIB regs */
-	uint32_t			buid_lsi;
-	uint32_t			buid_msi;
-	uint64_t			io_base;
-	uint64_t			m32_base;
-	uint64_t			m64_base;
-	int64_t				ecap;	/* cached PCI-E cap offset */
-	int64_t				aercap; /* cached AER ecap offset */
-	uint64_t			lxive_cache[8];
-	uint64_t			mxive_cache[256];
-	uint64_t			mve_cache[256];
-	uint64_t			peltm_cache[128];
-	uint64_t			peltv_lo_cache[128];
-	uint64_t			peltv_hi_cache[128];
-	uint64_t			tve_lo_cache[128];
-	uint64_t			tve_hi_cache[128];
-	uint64_t			iod_cache[128];
-	uint64_t			m32d_cache[128];
-	uint64_t			m64b_cache[16];
-	uint64_t			m64d_cache[128];
-	bool				err_pending;
-	struct p7ioc_err		err;
-	struct p7ioc			*ioc;
-	struct phb			phb;
-};
-
-static inline struct p7ioc_phb *phb_to_p7ioc_phb(struct phb *phb)
-{
-	return container_of(phb, struct p7ioc_phb, phb);
-}
-
-static inline bool p7ioc_phb_err_pending(struct p7ioc_phb *p)
-{
-	return p->err_pending;
-}
-
-static inline void p7ioc_phb_set_err_pending(struct p7ioc_phb *p, bool pending)
-{
-	if (!pending) {
-		p->err.err_src   = P7IOC_ERR_SRC_NONE;
-		p->err.err_class = P7IOC_ERR_CLASS_NONE;
-		p->err.err_bit   = -1;
-	}
-
-	p->err_pending = pending;
-}
-
-/*
- * State structure for P7IOC IO HUB
- */
-struct p7ioc {
-	/* Device node */
-	struct dt_node			*dt_node;
-
-	/* MMIO regs */
-	void				*regs;
-
-	/* Main MMIO window from GX for registers & PCI IO space */
-	uint64_t			mmio1_win_start;
-	uint64_t			mmio1_win_size;
-
-	/* Secondary MMIO window for PCI MMIO space */
-	uint64_t			mmio2_win_start;
-	uint64_t			mmio2_win_size;
-
-	/* BUID base for the PHB. This does include the top bits
-	 * (chip, GX bus ID, etc...). This is initialized from the
-	 * SPIRA. It does not contain the offset 0x10 for RGC
-	 * interrupts.
-	 *
-	 * The OPAL-defined "interrupt-base" property will contain
-	 * the RGC BUID, not this base value, since this is the real
-	 * starting point of interrupts for the IOC and we don't want
-	 * to cover the BUID 0..f gap which is reserved for P7 on-chip
-	 * interrupt sources.
-	 */
-	uint32_t			buid_base;
-	uint32_t			rgc_buid;
-
-	/* XIVT cache for RGC interrupts */
-	uint64_t			xive_cache[16];
-	bool				err_pending;
-	struct p7ioc_err		err;
-
-	/* PHB array & presence detect */
-	struct p7ioc_phb		phbs[P7IOC_NUM_PHBS];
-	uint8_t				phb_pdt;
-	   
-	struct io_hub			hub;
-};
-
-static inline struct p7ioc *iohub_to_p7ioc(struct io_hub *hub)
-{
-	return container_of(hub, struct p7ioc, hub);
-}
-
-static inline bool p7ioc_err_pending(struct p7ioc *ioc)
-{
-	return ioc->err_pending;
-}
-
-static inline void p7ioc_set_err_pending(struct p7ioc *ioc, bool pending)
-{
-	if (!pending) {
-		ioc->err.err_src   = P7IOC_ERR_SRC_NONE;
-		ioc->err.err_class = P7IOC_ERR_CLASS_NONE;
-		ioc->err.err_bit   = -1;
-	}
-
-	ioc->err_pending = pending;
-}
-
-static inline bool p7ioc_phb_enabled(struct p7ioc *ioc, unsigned int phb)
-{
-	return !!(ioc->phb_pdt & (0x80 >> phb));
-}
-
-extern int64_t p7ioc_inits(struct p7ioc *ioc);
-
-extern void p7ioc_phb_setup(struct p7ioc *ioc, uint8_t index);
-extern int64_t p7ioc_phb_init(struct p7ioc_phb *p);
-
-extern bool p7ioc_check_LEM(struct p7ioc *ioc, uint16_t *pci_error_type,
-			    uint16_t *severity);
-extern int64_t p7ioc_phb_get_xive(struct p7ioc_phb *p, uint32_t isn,
-				  uint16_t *server, uint8_t *prio);
-extern int64_t p7ioc_phb_set_xive(struct p7ioc_phb *p, uint32_t isn,
-				  uint16_t server, uint8_t prio);
-extern void p7ioc_reset(struct io_hub *hub);
-extern void p7ioc_phb_reset(struct phb *phb);
-
-#endif /* __P7IOC_H */
diff --git a/include/processor.h b/include/processor.h
index edcc210..b759752 100644
--- a/include/processor.h
+++ b/include/processor.h
@@ -19,7 +19,7 @@
 
 #include <bitutils.h>
 
-/* P7 MSR bits */
+/* MSR bits */
 #define MSR_SF		PPC_BIT(0)	/* 64-bit mode */
 #define MSR_HV		PPC_BIT(3)	/* Hypervisor mode */
 #define MSR_VEC		PPC_BIT(38)	/* VMX enable */
@@ -41,7 +41,6 @@
 /* PIR */
 #define SPR_PIR_P9_MASK		0x7fff	/* Mask of implemented bits */
 #define SPR_PIR_P8_MASK		0x1fff	/* Mask of implemented bits */
-#define SPR_PIR_P7_MASK		0x03ff	/* Mask of implemented bits */
 
 /* SPR register definitions */
 #define SPR_DSCR	0x011	/* RW: Data stream control reg */
@@ -96,12 +95,7 @@
 
 /* Bits in LPCR */
 
-/* Powersave Exit Cause Enable is different for P7 and P8 */
-#define SPR_LPCR_P7_PECE	PPC_BITMASK(49,51)
-#define SPR_LPCR_P7_PECE0	PPC_BIT(49)   /* Wake on external interrupts */
-#define SPR_LPCR_P7_PECE1	PPC_BIT(50)   /* Wake on decrementer */
-#define SPR_LPCR_P7_PECE2	PPC_BIT(51)   /* Wake on MCs, HMIs, etc... */
-
+/* Powersave Exit Cause Enable is different on each generation */
 #define SPR_LPCR_P8_PECE	PPC_BITMASK(47,51)
 #define SPR_LPCR_P8_PECE0	PPC_BIT(47)   /* Wake on priv doorbell */
 #define SPR_LPCR_P8_PECE1	PPC_BIT(48)   /* Wake on hv doorbell */
@@ -200,8 +194,6 @@
 #define PVR_VERS_MIN(_pvr)	GETFIELD(SPR_PVR_VERS_MIN, _pvr)
 
 /* PVR definitions */
-#define PVR_TYPE_P7	0x003f
-#define PVR_TYPE_P7P	0x004a
 #define PVR_TYPE_P8E	0x004b /* Murano */
 #define PVR_TYPE_P8	0x004d /* Venice */
 #define PVR_TYPE_P8NVL	0x004c /* Naples */
diff --git a/include/psi.h b/include/psi.h
index 79555ec..ad56ce1 100644
--- a/include/psi.h
+++ b/include/psi.h
@@ -54,7 +54,7 @@
 #define PSIHB_CR			0x20
 #define   PSIHB_CR_FSP_CMD_ENABLE	PPC_BIT(0)
 #define   PSIHB_CR_FSP_MMIO_ENABLE	PPC_BIT(1)
-#define   PSIHB_CR_TCE_ENABLE		PPC_BIT(2)	/* P7 only */
+#define   PSIHB_CR_TCE_ENABLE		PPC_BIT(2)
 #define   PSIHB_CR_FSP_IRQ_ENABLE	PPC_BIT(3)
 #define   PSIHB_CR_FSP_ERR_RSP_ENABLE	PPC_BIT(4)
 #define   PSIHB_CR_PSI_LINK_ENABLE	PPC_BIT(5)
@@ -81,9 +81,6 @@
 /* PSI Status / Error Mask Register */
 #define PSIHB_SEMR			0x28
 
-/* XIVR and BUID used for PSI interrupts on P7 */
-#define PSIHB_XIVR			0x30
-
 /* XIVR and BUID used for PSI interrupts on P8 */
 #define PSIHB_XIVR_FSP			0x30
 #define PSIHB_XIVR_OCC			0x60
@@ -123,13 +120,6 @@
 /*
  * PSI Host Bridge Registers (XSCOM)
  */
-#define PSIHB_XSCOM_P7_HBBAR		0x9
-#define   PSIHB_XSCOM_P7_HBBAR_EN	PPC_BIT(28)
-#define PSIHB_XSCOM_P7_HBCSR		0xd
-#define PSIHB_XSCOM_P7_HBCSR_SET	0x11
-#define PSIHB_XSCOM_P7_HBCSR_CLR	0x12
-#define   PSIHB_XSCOM_P7_HBSCR_FSP_IRQ 	PPC_BIT(13)
-
 #define PSIHB_XSCOM_P8_BASE		0xa
 #define   PSIHB_XSCOM_P8_HBBAR_EN	PPC_BIT(63)
 #define PSIHB_XSCOM_P8_HBCSR		0xe
@@ -166,8 +156,6 @@
 /*
  * Layout of the PSI DMA address space
  *
- * On P7, we instanciate a TCE table of 16K TCEs mapping 64M
- *
  * On P8, we use a larger mapping of 256K TCEs which provides
  * us with a 1G window in order to fit the trace buffers
  *
diff --git a/include/skiboot.h b/include/skiboot.h
index d70d828..1b3bacb 100644
--- a/include/skiboot.h
+++ b/include/skiboot.h
@@ -107,7 +107,6 @@ void _prlog(int log_level, const char* fmt, ...) __attribute__((format (printf,
 /* Processor generation */
 enum proc_gen {
 	proc_gen_unknown,
-	proc_gen_p7,		/* P7 and P7+ */
 	proc_gen_p8,
 	proc_gen_p9,
 };
@@ -203,7 +202,6 @@ extern void copy_sreset_vector(void);
 extern void copy_sreset_vector_fast_reboot(void);
 
 /* Various probe routines, to replace with an initcall system */
-extern void probe_p7ioc(void);
 extern void probe_phb3(void);
 extern void probe_phb4(void);
 extern int preload_capp_ucode(void);