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| author | Gavin Shan <gwshan@linux.vnet.ibm.com> | 2015-07-17 09:12:31 +1000 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2015-08-14 14:00:17 +1000 |
| commit | 9af2d0b1bd46cb35026f7eb9fa3b1e4d8e131534 (patch) | |
| tree | 65f26a7ae8088d146893193624ac2660ee0a4410 /include | |
| parent | affcb6471add85007e4f284f0f79f65722488f7f (diff) | |
| download | skiboot-9af2d0b1bd46cb35026f7eb9fa3b1e4d8e131534.zip skiboot-9af2d0b1bd46cb35026f7eb9fa3b1e4d8e131534.tar.gz skiboot-9af2d0b1bd46cb35026f7eb9fa3b1e4d8e131534.tar.bz2 | |
hw/phb3: Change reserved PE to 255
Currently, we have reserved PE#0 to which all RIDs are mapped prior
to PE assignment request from kernel. The last M64 BAR is configured
to have shared mode. So we have to cut off the first M64 segment,
which corresponds to reserved PE#0 in kernel. If the first BAR
(for example PF's IOV BAR) requires huge alignment in kernel, we
have to waste huge M64 space to accomodate the alignment. If we
have reserved PE#256, the waste of M64 space will be avoided.
Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/phb3.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/phb3.h b/include/phb3.h index ea3ad87..c15f5d2 100644 --- a/include/phb3.h +++ b/include/phb3.h @@ -148,6 +148,7 @@ struct rtt_entry { * capability register later. */ #define PHB3_MAX_PE_NUM 256 +#define PHB3_RESERVED_PE_NUM 255 /* * State structure for a PHB |