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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2016-12-22 14:16:42 +1100
committerStewart Smith <stewart@linux.vnet.ibm.com>2017-01-05 15:41:01 +1100
commit9b95afb521b1e2634e518b1851e2c902e83a888a (patch)
tree8b74d883332f8d0d64d00b75947797247ed5fd98 /include
parent6e1b56ecf2fa9e5537887879852b53186341f4ba (diff)
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xive: Implement xive_reset
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [stewart@linux.vnet.ibm.com: fix build failure on older GCC - e.g. 4.8] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'include')
-rw-r--r--include/xive.h6
1 files changed, 4 insertions, 2 deletions
diff --git a/include/xive.h b/include/xive.h
index 7db7ee0..c7b96fa 100644
--- a/include/xive.h
+++ b/include/xive.h
@@ -299,12 +299,14 @@
*/
#define TM_SPC_ACK_EBB 0x800 /* Load8 ack EBB to reg*/
#define TM_SPC_ACK_OS_REG 0x810 /* Load16 ack OS irq to reg */
-#define TM_SPC_ACK_OS_EL 0xc10 /* Store8 ack OS irq to even line */
#define TM_SPC_PUSH_USR_CTX 0x808 /* Store32 Push/Validate user context */
#define TM_SPC_PULL_USR_CTX 0x808 /* Load32 Pull/Invalidate user context */
-#define TM_SPC_PULL_USR_CTX_OL 0xc08 /* Store8 Pull/Inval usr ctx to odd line */
#define TM_SPC_SET_OS_PENDING 0x812 /* Store8 Set OS irq pending bit */
+#define TM_SPC_PULL_OS_CTX 0x818 /* Load32/Load64 Pull/Invalidate OS context to reg */
+#define TM_SPC_PULL_POOL_CTX 0x828 /* Load32/Load64 Pull/Invalidate Pool context to reg*/
#define TM_SPC_ACK_HV_REG 0x830 /* Load16 ack HV irq to reg */
+#define TM_SPC_PULL_USR_CTX_OL 0xc08 /* Store8 Pull/Inval usr ctx to odd line */
+#define TM_SPC_ACK_OS_EL 0xc10 /* Store8 ack OS irq to even line */
#define TM_SPC_ACK_HV_POOL_EL 0xc20 /* Store8 ack HV evt pool to even line */
#define TM_SPC_ACK_HV_EL 0xc30 /* Store8 ack HV irq to even line */
/* XXX more... */