sparse: Make tree 'constant is so big' warning clean

Signed-off-by: Stewart Smith <stewart@linux.ibm.com>

4 files changed, 27 insertions, 27 deletions

diff --git a/include/npu-regs.h b/include/npu-regs.h
index 4f1a19c..0ccc40f 100644
--- a/include/npu-regs.h
+++ b/include/npu-regs.h
@@ -178,60 +178,60 @@
 #define PL_MMIO_ADDR(reg) (((reg >> 32) & 0xfffffull) << 1)
 
 /* PHY register scom offsets & fields */
-#define RX_PR_CNTL_PL		0x0002180000000000
+#define RX_PR_CNTL_PL		0x0002180000000000UL
 #define	  RX_PR_RESET		PPC_BIT(63)
 
-#define TX_MODE1_PL		0x0004040000000000
+#define TX_MODE1_PL		0x0004040000000000UL
 #define   TX_LANE_PDWN		PPC_BIT(48)
 
-#define TX_MODE2_PL		0x00040c0000000000
+#define TX_MODE2_PL		0x00040c0000000000UL
 #define   TX_RXCAL		PPC_BIT(57)
 #define   TX_UNLOAD_CLK_DISABLE PPC_BIT(56)
 
-#define TX_CNTL_STAT2		0x00041c0000000000
+#define TX_CNTL_STAT2		0x00041c0000000000UL
 #define   TX_FIFO_INIT		PPC_BIT(48)
 
-#define RX_BANK_CONTROLS	0x0000f80000000000
+#define RX_BANK_CONTROLS	0x0000f80000000000UL
 #define   RX_LANE_ANA_PDWN	PPC_BIT(54)
 
-#define RX_MODE			0x0002000000000000
+#define RX_MODE			0x0002000000000000UL
 #define   RX_LANE_DIG_PDWN	PPC_BIT(48)
 
-#define RX_PR_MODE		0x0002100000000000
+#define RX_PR_MODE		0x0002100000000000UL
 #define   RX_PR_PHASE_STEP	PPC_BITMASK(60, 63)
 
-#define RX_A_DAC_CNTL		0x0000080000000000
+#define RX_A_DAC_CNTL		0x0000080000000000UL
 #define   RX_PR_IQ_RES_SEL	PPC_BITMASK(58, 60)
 
-#define RX_LANE_BUSY_VEC_0_15	0x000b000000000000
-#define TX_FFE_TOTAL_2RSTEP_EN	0x000c240000000000
+#define RX_LANE_BUSY_VEC_0_15	0x000b000000000000UL
+#define TX_FFE_TOTAL_2RSTEP_EN	0x000c240000000000UL
 #define   TX_FFE_TOTAL_ENABLE_P_ENC	PPC_BITMASK(49,55)
 #define   TX_FFE_TOTAL_ENABLE_N_ENC	PPC_BITMASK(57,63)
-#define TX_FFE_PRE_2RSTEP_SEL	0x000c2c0000000000
+#define TX_FFE_PRE_2RSTEP_SEL	0x000c2c0000000000UL
 #define   TX_FFE_PRE_P_SEL_ENC		PPC_BITMASK(51,54)
 #define   TX_FFE_PRE_N_SEL_ENC		PPC_BITMASK(59,62)
-#define TX_FFE_MARGIN_2RSTEP_SEL 0x000c34000000000
+#define TX_FFE_MARGIN_2RSTEP_SEL 0x000c34000000000UL
 #define   TX_FFE_MARGIN_PU_P_SEL_ENC	PPC_BITMASK(51,55)
 #define   TX_FFE_MARGIN_PD_N_SEL_ENC	PPC_BITMASK(59,63)
-#define TX_IORESET_VEC_0_15	0x000d2c0000000000
-#define TX_IMPCAL_PB		0x000f040000000000
+#define TX_IORESET_VEC_0_15	0x000d2c0000000000UL
+#define TX_IMPCAL_PB		0x000f040000000000UL
 #define   TX_ZCAL_REQ			PPC_BIT(49)
 #define	  TX_ZCAL_DONE			PPC_BIT(50)
 #define   TX_ZCAL_ERROR			PPC_BIT(51)
-#define TX_IMPCAL_NVAL_PB	0x000f0c0000000000
+#define TX_IMPCAL_NVAL_PB	0x000f0c0000000000UL
 #define   TX_ZCAL_N			PPC_BITMASK(48,56)
-#define TX_IMPCAL_PVAL_PB	0x000f140000000000
+#define TX_IMPCAL_PVAL_PB	0x000f140000000000UL
 #define   TX_ZCAL_P			PPC_BITMASK(48,56)
-#define RX_EO_STEP_CNTL_PG	0x0008300000000000
+#define RX_EO_STEP_CNTL_PG	0x0008300000000000UL
 #define   RX_EO_ENABLE_LATCH_OFFSET_CAL	PPC_BIT(48)
 #define   RX_EO_ENABLE_CM_COARSE_CAL	PPC_BIT(57)
-#define RX_RUN_LANE_VEC_0_15   	0x0009b80000000000
-#define RX_RECAL_ABORT_VEC_0_15 0x0009c80000000000
-#define RX_IORESET_VEC_0_15	0x0009d80000000000
-#define RX_EO_RECAL_PG		0x000a800000000000
-#define RX_INIT_DONE_VEC_0_15	0x000ac00000000000
-#define TX_IMPCAL_SWO1_PB	0x000f240000000000
+#define RX_RUN_LANE_VEC_0_15   	0x0009b80000000000UL
+#define RX_RECAL_ABORT_VEC_0_15 0x0009c80000000000UL
+#define RX_IORESET_VEC_0_15	0x0009d80000000000UL
+#define RX_EO_RECAL_PG		0x000a800000000000UL
+#define RX_INIT_DONE_VEC_0_15	0x000ac00000000000UL
+#define TX_IMPCAL_SWO1_PB	0x000f240000000000UL
 #define   TX_ZCAL_SWO_EN		PPC_BIT(48)
-#define TX_IMPCAL_SWO2_PB	0x000f2c0000000000
+#define TX_IMPCAL_SWO2_PB	0x000f2c0000000000UL
 
 #endif /* __NPU_REGS_H */
diff --git a/include/npu2-regs.h b/include/npu2-regs.h
index 8273b2b..7171e9e 100644
--- a/include/npu2-regs.h
+++ b/include/npu2-regs.h
@@ -758,7 +758,7 @@ void npu2_scom_write(uint64_t gcid, uint64_t scom_base,
 
 /* Registers and bits used to clear the L2 and L3 cache */
 #define L2_PRD_PURGE_CMD_REG 			0x1080E
-#define L2_PRD_PURGE_CMD_REG_BUSY 		0x0040000000000000
+#define L2_PRD_PURGE_CMD_REG_BUSY 		0x0040000000000000UL
 #define L2_PRD_PURGE_CMD_TYPE_MASK		PPC_BIT(1) | PPC_BIT(2) | PPC_BIT(3) | PPC_BIT(4)
 #define L2_PRD_PURGE_CMD_TRIGGER		PPC_BIT(0)
 #define L2CAC_FLUSH				0x0
diff --git a/include/opal-internal.h b/include/opal-internal.h
index 2ce25ad..60d7f7b 100644
--- a/include/opal-internal.h
+++ b/include/opal-internal.h
@@ -100,7 +100,7 @@ static inline bool opal_addr_valid(const void *addr)
 	unsigned long val = (unsigned long)addr;
 	if ((val >> 60) != 0xc && (val >> 60) != 0x0)
 		return false;
-	val &= ~0xf000000000000000;
+	val &= ~0xf000000000000000UL;
 	if (val > top_of_ram)
 		return false;
 	return true;
diff --git a/include/pci-slot.h b/include/pci-slot.h
index 708374b..7c5fd60 100644
--- a/include/pci-slot.h
+++ b/include/pci-slot.h
@@ -192,7 +192,7 @@ struct pci_slot {
 	void			*data;
 };
 
-#define PCI_SLOT_ID_PREFIX	0x8000000000000000
+#define PCI_SLOT_ID_PREFIX	0x8000000000000000UL
 #define PCI_SLOT_ID(phb, bdfn)	\
 	(PCI_SLOT_ID_PREFIX | ((uint64_t)(bdfn) << 16) | (phb)->opal_id)
 #define PCI_PHB_SLOT_ID(phb)	((phb)->opal_id)