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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2016-07-24 09:32:10 +1000
committerStewart Smith <stewart@linux.vnet.ibm.com>2016-10-17 10:33:28 +1100
commit0279d8951ead549fdebce93130a2f6c673081862 (patch)
treeb0fee12867dbf0a4796ec98b3d4b12907d604ab0 /include
parent8110b0595f0de2df18a06e8e9aff66db45872fa7 (diff)
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Fast reboot for P8
This is an experimental patch that implements "Fast reboot" on P8 machines. The basic idea is that when the OS calls OPAL reboot, we gather all the threads in the system using a combination of patching the reset vector and soft-resetting them, then cleanup a few bits of hardware (we do re-probe PCIe for example), and reload & restart the bootloader. For Trusted Boot, this means we *add* measurements to the TPM, so you will get *different* PCR values as compared to a full IPL. This makes sense as if you want to be sure you are running something known then, well, do a full IPL as soft reset should never be trusted to clear any malicious code. This is very experimental and needs a lot of testing and also auditing code for other bits of HW that might need to be cleaned up. BenH TODO: I also need to check if we are properly PERST'ing PCI devices. This is partially based on old code I had to do that on P7. I only support it on P8 though as there are issues with the PSI interrupts on P7 that cannot be reliably solved. Even though this should be considered somewhat experimental, we've had a lot of success on a variety of machines. Dozens/hundreds of reboots across Tuleta, Garrison and Habanero. Currently, we've hidden it behind a NVRAM config option, which *is* liable to change in the future (to ensure that only those who know what they're doing enable it) You can enable the experimental support via nvram option: nvram -p ibm,skiboot --update-config experimental-fast-reset=feeling-lucky Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [stewart@linux.vnet.ibm.com: hide behind nvram option, include Mambo fixes from Mikey] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'include')
-rw-r--r--include/config.h3
-rw-r--r--include/cpu.h1
-rw-r--r--include/processor.h1
-rw-r--r--include/skiboot.h9
4 files changed, 10 insertions, 4 deletions
diff --git a/include/config.h b/include/config.h
index 2524570..f6572b0 100644
--- a/include/config.h
+++ b/include/config.h
@@ -72,9 +72,6 @@
*/
//#define FORCE_DUMMY_CONSOLE 1
-/* Enable this to do fast resets. Currently unreliable... */
-//#define ENABLE_FAST_RESET 1
-
/* Enable this to make fast reboot clear memory */
//#define FAST_REBOOT_CLEARS_MEMORY 1
diff --git a/include/cpu.h b/include/cpu.h
index 341e73d..f649a13 100644
--- a/include/cpu.h
+++ b/include/cpu.h
@@ -66,6 +66,7 @@ struct cpu_thread {
bool in_mcount;
bool in_poller;
bool in_reinit;
+ bool in_fast_sleep;
bool in_sleep;
bool in_idle;
uint32_t hbrt_spec_wakeup; /* primary only */
diff --git a/include/processor.h b/include/processor.h
index 4b11702..3942268 100644
--- a/include/processor.h
+++ b/include/processor.h
@@ -164,6 +164,7 @@
/* Bits in HID0 */
#define SPR_HID0_POWER8_4LPARMODE PPC_BIT(2)
#define SPR_HID0_POWER8_2LPARMODE PPC_BIT(6)
+#define SPR_HID0_POWER8_DYNLPARDIS PPC_BIT(15)
#define SPR_HID0_POWER8_HILE PPC_BIT(19)
#define SPR_HID0_POWER9_HILE PPC_BIT(4)
#define SPR_HID0_POWER8_ENABLE_ATTN PPC_BIT(31)
diff --git a/include/skiboot.h b/include/skiboot.h
index 2a9f5e2..2ef7677 100644
--- a/include/skiboot.h
+++ b/include/skiboot.h
@@ -190,12 +190,14 @@ extern unsigned long get_symbol(unsigned long addr,
char **sym, char **sym_end);
/* Fast reboot support */
-extern void fast_reset(void);
+extern void fast_reboot(void);
extern void __noreturn __secondary_cpu_entry(void);
extern void __noreturn load_and_boot_kernel(bool is_reboot);
extern void cleanup_tlb(void);
extern void init_shared_sprs(void);
extern void init_replicated_sprs(void);
+extern bool start_preload_kernel(void);
+extern void copy_exception_vectors(void);
extern void setup_reset_vector(void);
/* Various probe routines, to replace with an initcall system */
@@ -269,6 +271,11 @@ extern void slw_update_timer_expiry(uint64_t new_target);
/* Is SLW timer available ? */
extern bool slw_timer_ok(void);
+/* Patch SPR in SLW image */
+extern int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val);
+
+extern void fast_sleep_exit(void);
+
/* Fallback fake RTC */
extern void fake_rtc_init(void);