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| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2016-08-09 16:38:10 +1000 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2016-08-11 19:54:22 +1000 |
| commit | f605be73d7b1c4a32a66824d3c02470f540636bc (patch) | |
| tree | aa15668ec33934473349eb599945b8d3bdd1f68b /include | |
| parent | 586939633523774acf1bda2ce64f3e81d7ceb724 (diff) | |
| download | skiboot-f605be73d7b1c4a32a66824d3c02470f540636bc.zip skiboot-f605be73d7b1c4a32a66824d3c02470f540636bc.tar.gz skiboot-f605be73d7b1c4a32a66824d3c02470f540636bc.tar.bz2 | |
lpc: Add P9 LPC interrupts support
We currently don't exploit the new MUX that allow to spread them
around different PSI interrupts, they all go to LPC#0
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/lpc.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/include/lpc.h b/include/lpc.h index a79d256..42c4755 100644 --- a/include/lpc.h +++ b/include/lpc.h @@ -59,6 +59,7 @@ /* Routines for accessing the LPC bus on Power8 */ extern void lpc_init(void); +extern void lpc_init_interrupts(void); /* Check for a default bus */ extern bool lpc_present(void); @@ -72,6 +73,9 @@ extern bool lpc_ok(void); /* Handle the interrupt from the LPC controller */ extern void lpc_interrupt(uint32_t chip_id); +/* On P9, we have a different route for SerIRQ */ +extern void lpc_serirq(uint32_t chip_id, uint32_t index); + /* Call all external handlers */ extern void lpc_all_interrupts(uint32_t chip_id); @@ -100,6 +104,9 @@ extern int64_t lpc_read(enum OpalLPCAddressType addr_type, uint32_t addr, /* Mark LPC bus as used by console */ extern void lpc_used_by_console(void); +/* Route SerIRQs to specific PSI/LPC interrupt sources */ +void lpc_route_serirq(uint32_t chip_id, uint32_t sirq, uint32_t psi_idx); + /* * Simplified big endian FW accessors */ |