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| author | Frederic Barrat <fbarrat@linux.vnet.ibm.com> | 2017-06-06 16:59:45 +0200 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-06-07 19:56:47 +1000 |
| commit | 5201e811bd19eebc3fbeaa11c75fed12bc8c31fe (patch) | |
| tree | 2bf3001be6348c30d88511cf7c2e1fd704af6411 /include | |
| parent | b0809b89ecdf430c9f6e0272fb4cf0dc01a4989d (diff) | |
| download | skiboot-5201e811bd19eebc3fbeaa11c75fed12bc8c31fe.zip skiboot-5201e811bd19eebc3fbeaa11c75fed12bc8c31fe.tar.gz skiboot-5201e811bd19eebc3fbeaa11c75fed12bc8c31fe.tar.bz2 | |
phb4: Activate shared PCI slot on witherspoon
Witherspoon systems come with a 'shared' PCI slot: physically, it
looks like a x16 slot, but it's actually two x8 slots connected to two
PHBs of two different chips. Taking advantage of it requires some
logic on the PCI adapter. Only the Mellanox CX5 adapter is known to
support it at the time of this writing.
This patch enables support for the shared slot on witherspoon if a x16
adapter is detected. Each x8 slot has a presence bit, so both bits
need to be set for the activation to take place. Slot sharing is
activated through a gpio.
Note that there's no easy way to be sure that the card is indeed a
shared-slot compatible PCI adapter and not a normal x16 card. Plugging
a normal x16 adapter on the shared slot should be avoided on
witherspoon, as the link won't train on the second slot, resulting in
a timeout and a longer boot time. Only the first slot is usable and
the x16 adapter will end up using only half the lines.
If the PCI card plugged on the physical slot is only x8 (or less),
then the presence bit of the second slot is not set, so this patch
does nothing. The x8 (or less) adapter should work like on any other
physical slot.
Signed-off-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>
[stewart@linux.vnet.ibm.com: re-org code, move into platform file]
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/phb4.h | 7 | ||||
| -rw-r--r-- | include/platform.h | 5 | ||||
| -rw-r--r-- | include/xscom-p9-regs.h | 3 |
3 files changed, 15 insertions, 0 deletions
diff --git a/include/phb4.h b/include/phb4.h index bed6eef..3ec8a5b 100644 --- a/include/phb4.h +++ b/include/phb4.h @@ -306,4 +306,11 @@ static inline void phb4_set_err_pending(struct phb4 *p, bool pending) p->err_pending = pending; } +#define PHB4_PER_CHIP 6 /* Max 6 PHBs per chip on p9 */ + +static inline int phb4_get_opal_id(unsigned int chip_id, unsigned int index) +{ + return chip_id * PHB4_PER_CHIP + index; +} + #endif /* __PHB4_H */ diff --git a/include/platform.h b/include/platform.h index 9133204..4dcdb33 100644 --- a/include/platform.h +++ b/include/platform.h @@ -101,6 +101,11 @@ struct platform { void (*pci_setup_phb)(struct phb *phb, unsigned int index); /* + * This is called before resetting the PHBs (lift PERST) and + * probing the devices. The PHBs have already been initialized. + */ + void (*pre_pci_fixup)(void); + /* * Called during PCI scan for each device. For bridges, this is * called before its children are probed. This is called for * every device and for the PHB itself with a NULL pd though diff --git a/include/xscom-p9-regs.h b/include/xscom-p9-regs.h index 7da404b..4738e81 100644 --- a/include/xscom-p9-regs.h +++ b/include/xscom-p9-regs.h @@ -18,4 +18,7 @@ #define P9X_EX_NCU_DARN_BAR 0x11011 #define P9X_EX_NCU_DARN_BAR_EN PPC_BIT(0) +#define P9_GPIO_DATA_OUT_ENABLE 0x00000000000B0054ull +#define P9_GPIO_DATA_OUT 0x00000000000B0051ull + #endif /* __XSCOM_P9_REGS_H__ */ |