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| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2017-04-27 15:56:39 +0200 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-04-28 15:11:15 +1000 |
| commit | 0bca35a2570f1dc24c8eb6a36113e7bce28bdc99 (patch) | |
| tree | f18cd8e15de43661c4a0e3b325c48f0b1f355033 /include | |
| parent | 0aff8c2f9e6d60a71bdbd7c6e06df3e4f1debccd (diff) | |
| download | skiboot-0bca35a2570f1dc24c8eb6a36113e7bce28bdc99.zip skiboot-0bca35a2570f1dc24c8eb6a36113e7bce28bdc99.tar.gz skiboot-0bca35a2570f1dc24c8eb6a36113e7bce28bdc99.tar.bz2 | |
xive+phb4: Fix exposing trigger page to Linux
We currently don't expose the trigger page of MSIs to Linux which
breaks re-sending of a queued one. To fix that properly we need
to understand out a subtle API complication:
- The "internal" XIVE_SRC_TRIGGER_PAGE indicates that a trigger
page is supported, whether it's the same page as the EOI page
or not.
- The "external" OPAL_XIVE_IRQ_TRIGGER_PAGE indicates that a
*separate* trigger page exists. To know if triggers are supported
the caller should simply check if a valid (non-0) value is returned
in "out_trig_page" of opal_xive_get_irq_info().
So PHB4 must set XIVE_SRC_TRIGGER_PAGE for MSIs and the xive code
needs to do the "right" thing for setting whether
OPAL_XIVE_IRQ_TRIGGER_PAGE should be set or not.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/xive.h | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/include/xive.h b/include/xive.h index 06aad8b..d2ef1d9 100644 --- a/include/xive.h +++ b/include/xive.h @@ -447,11 +447,15 @@ uint64_t xive_get_notify_port(uint32_t chip_id, uint32_t ent); uint32_t xive_get_notify_base(uint32_t girq); /* Internal IRQ flags */ -#define XIVE_SRC_TRIGGER_PAGE 0x01 -#define XIVE_SRC_EOI_PAGE1 0x02 -#define XIVE_SRC_STORE_EOI 0x04 -#define XIVE_SRC_LSI 0x08 -#define XIVE_SRC_SHIFT_BUG 0x10 +#define XIVE_SRC_TRIGGER_PAGE 0x01 /* Trigger page exist (either separate + * or not, so different from the OPAL + * flag which is only set when the + * trigger page is separate). + */ +#define XIVE_SRC_EOI_PAGE1 0x02 /* EOI on the second page */ +#define XIVE_SRC_STORE_EOI 0x04 /* EOI using stores supported */ +#define XIVE_SRC_LSI 0x08 /* Interrupt is an LSI */ +#define XIVE_SRC_SHIFT_BUG 0x10 /* ESB update offset << 4 */ struct irq_source_ops; void xive_register_hw_source(uint32_t base, uint32_t count, uint32_t shift, |