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| author | Alistair Popple <alistair@popple.id.au> | 2018-01-11 15:28:51 +1100 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2018-01-14 23:48:48 -0600 |
| commit | 695bb562a315d4402fe3e82e93ed72265cefa8db (patch) | |
| tree | 4ff54f18aeb908066c66b1ef9d1b31feedac6cfb /include | |
| parent | 8cbc15556621c08634915a371f688586c7aabbcb (diff) | |
| download | skiboot-695bb562a315d4402fe3e82e93ed72265cefa8db.zip skiboot-695bb562a315d4402fe3e82e93ed72265cefa8db.tar.gz skiboot-695bb562a315d4402fe3e82e93ed72265cefa8db.tar.bz2 | |
npu2.c: Add PE error detection
Invalid accesses from the GPU can cause a specific PE to be frozen by the
NPU. Add an interrupt handler which reports the frozen PE to the operating
system via as an EEH event.
Signed-off-by: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/npu2-regs.h | 17 |
1 files changed, 1 insertions, 16 deletions
diff --git a/include/npu2-regs.h b/include/npu2-regs.h index fdaad19..e739ac5 100644 --- a/include/npu2-regs.h +++ b/include/npu2-regs.h @@ -342,22 +342,7 @@ void npu2_write_mask(struct npu2 *p, uint64_t reg, uint64_t val, uint64_t mask); #define NPU2_MISC_BRICK_BDF2PE_MAP_ENABLE PPC_BIT(0) #define NPU2_MISC_BRICK_BDF2PE_MAP_PE PPC_BITMASK(4,7) #define NPU2_MISC_BRICK_BDF2PE_MAP_BDF PPC_BITMASK(8,23) -#define NPU2_MISC_PESTB00 NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_MISC, 0x200) -#define NPU2_MISC_PESTB01 NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_MISC, 0x208) -#define NPU2_MISC_PESTB02 NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_MISC, 0x210) -#define NPU2_MISC_PESTB03 NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_MISC, 0x218) -#define NPU2_MISC_PESTB04 NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_MISC, 0x220) -#define NPU2_MISC_PESTB05 NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_MISC, 0x228) -#define NPU2_MISC_PESTB06 NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_MISC, 0x230) -#define NPU2_MISC_PESTB07 NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_MISC, 0x238) -#define NPU2_MISC_PESTB08 NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_MISC, 0x240) -#define NPU2_MISC_PESTB09 NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_MISC, 0x248) -#define NPU2_MISC_PESTB10 NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_MISC, 0x250) -#define NPU2_MISC_PESTB11 NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_MISC, 0x258) -#define NPU2_MISC_PESTB12 NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_MISC, 0x260) -#define NPU2_MISC_PESTB13 NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_MISC, 0x268) -#define NPU2_MISC_PESTB14 NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_MISC, 0x270) -#define NPU2_MISC_PESTB15 NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_MISC, 0x278) +#define NPU2_MISC_PESTB(pe) NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_MISC, 0x200 + (pe)*8) #define NPU2_MISC_IRQ_LOG0 NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_MISC, 0x300) #define NPU2_MISC_IRQ_LOG01 NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_MISC, 0x308) #define NPU2_MISC_IRQ_LOG02 NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_MISC, 0x310) |