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| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2017-11-21 20:32:26 +1100 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-11-28 20:39:07 -0600 |
| commit | de82c2e0ece66b2c19d5d9cdc965c90c95fb9af3 (patch) | |
| tree | 36884e7dfb6520febf52c3f3b822a52b5d105f59 /include | |
| parent | ddc35b93fcadf624e9c60c4b9fefd83330748613 (diff) | |
| download | skiboot-de82c2e0ece66b2c19d5d9cdc965c90c95fb9af3.zip skiboot-de82c2e0ece66b2c19d5d9cdc965c90c95fb9af3.tar.gz skiboot-de82c2e0ece66b2c19d5d9cdc965c90c95fb9af3.tar.bz2 | |
xive: Implement "single escalation" feature
This adds a new VP flag to control the new DD2.0
"single escalation" feature.
This feature allows us to have a single escalation
interrupt per VP instead of one per queue.
It works by hijacking queue 7 (which is this no longer
usable when that is enabled) and exploiting two new
hardware bits that will:
- Make the normal queues (0..6) escalate unconditionally
thus ignoring the ESe bits.
- Route the above escalations to queue 7
- Have queue 7 silently escalate without notification
Thus the escalation of queue 7 becomes the one escalation
interrupt for all the other queues.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/xive.h | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/include/xive.h b/include/xive.h index 63ee77b..ae7bb0b 100644 --- a/include/xive.h +++ b/include/xive.h @@ -397,13 +397,14 @@ struct xive_ive { /* EQ */ struct xive_eq { uint32_t w0; -#define EQ_W0_VALID PPC_BIT32(0) -#define EQ_W0_ENQUEUE PPC_BIT32(1) -#define EQ_W0_UCOND_NOTIFY PPC_BIT32(2) -#define EQ_W0_BACKLOG PPC_BIT32(3) -#define EQ_W0_PRECL_ESC_CTL PPC_BIT32(4) -#define EQ_W0_ESCALATE_CTL PPC_BIT32(5) -#define EQ_W0_END_OF_INTR PPC_BIT32(6) +#define EQ_W0_VALID PPC_BIT32(0) /* "v" bit */ +#define EQ_W0_ENQUEUE PPC_BIT32(1) /* "q" bit */ +#define EQ_W0_UCOND_NOTIFY PPC_BIT32(2) /* "n" bit */ +#define EQ_W0_BACKLOG PPC_BIT32(3) /* "b" bit */ +#define EQ_W0_PRECL_ESC_CTL PPC_BIT32(4) /* "p" bit */ +#define EQ_W0_ESCALATE_CTL PPC_BIT32(5) /* "e" bit */ +#define EQ_W0_UNCOND_ESCALATE PPC_BIT32(6) /* "u" bit - DD2.0 */ +#define EQ_W0_SILENT_ESCALATE PPC_BIT32(7) /* "s" bit - DD2.0 */ #define EQ_W0_QSIZE PPC_BITMASK32(12,15) #define EQ_W0_SW0 PPC_BIT32(16) #define EQ_W0_FIRMWARE EQ_W0_SW0 /* Owned by FW */ |