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authorBalbir Singh <bsingharora@gmail.com>2017-11-30 23:50:50 +1100
committerStewart Smith <stewart@linux.vnet.ibm.com>2018-02-08 18:58:13 -0600
commitb57a5380aa489fa877b2d619225aea2602f20dca (patch)
tree73941de3165044209694aaab55bcf09592b3945c /include
parentb3e14c46ecb069b3076ca052e7180048dd863e5c (diff)
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hw/npu2: Implement logging HMI actions
Log HMI errors as step 1. OS will need to deduce and interpret the HMI event. Signed-off-by: Balbir Singh <bsingharora@gmail.com> Acked-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'include')
-rw-r--r--include/npu2-regs.h11
-rw-r--r--include/opal-api.h98
2 files changed, 109 insertions, 0 deletions
diff --git a/include/npu2-regs.h b/include/npu2-regs.h
index e739ac5..846c384 100644
--- a/include/npu2-regs.h
+++ b/include/npu2-regs.h
@@ -460,4 +460,15 @@ void npu2_write_mask(struct npu2 *p, uint64_t reg, uint64_t val, uint64_t mask);
#define NPU2_DD1_MISC_SCOM_IND_SCOM_DATA 0x38f
#define NPU2_MISC_SCOM_IND_SCOM_DATA 0x68f
+#define NPU2_FIR_OFFSET 0x40
+#define NPU2_FIR_MASK_OFFSET 0x3
+#define NPU2_FIR_ACTION0_OFFSET 0x6
+#define NPU2_FIR_ACTION1_OFFSET 0x7
+
+#define NPU2_FIR_REGISTER_0 0x0000000005013C00
+#define NPU2_FIR_REGISTER_1 0x0000000005013C40
+#define NPU2_FIR_REGISTER_2 0x0000000005013C80
+
+#define NPU2_TOTAL_FIR_REGISTERS 3
+
#endif /* __NPU2_REGS_H */
diff --git a/include/opal-api.h b/include/opal-api.h
index f0ed5f6..0bd5f17 100644
--- a/include/opal-api.h
+++ b/include/opal-api.h
@@ -732,6 +732,104 @@ enum OpalHMI_NestAccelXstopReason {
NX_CHECKSTOP_PBI_ISN_UE = 0x00002000,
};
+/*
+ * Can't use enums for 64 bit values, use #defines
+ */
+#define NPU2_CHECKSTOP_REG0_NTL_ARRAY_CE PPC_BIT(0)
+#define NPU2_CHECKSTOP_REG0_NTL_ARRAY_HDR_CE PPC_BIT(1)
+#define NPU2_CHECKSTOP_REG0_NTL_ARRAY_DATA_UE PPC_BIT(2)
+#define NPU2_CHECKSTOP_REG0_NTL_NVL_FLIT_PERR PPC_BIT(3)
+#define NPU2_CHECKSTOP_REG0_NTL_NVL_DATA_PERR PPC_BIT(4)
+#define NPU2_CHECKSTOP_REG0_NTL_NVL_PKT_MALFOR PPC_BIT(5)
+#define NPU2_CHECKSTOP_REG0_NTL_NVL_PKT_UNSUPPORTED PPC_BIT(6)
+#define NPU2_CHECKSTOP_REG0_NTL_NVL_CONFIG_ERR PPC_BIT(7)
+#define NPU2_CHECKSTOP_REG0_NTL_NVL_CRC_ERR PPC_BIT(8)
+#define NPU2_CHECKSTOP_REG0_NTL_PRI_ERR PPC_BIT(9)
+#define NPU2_CHECKSTOP_REG0_NTL_LOGIC_ERR PPC_BIT(10)
+#define NPU2_CHECKSTOP_REG0_NTL_LMD_POISON PPC_BIT(11)
+#define NPU2_CHECKSTOP_REG0_NTL_ARRAY_DATA_SUE PPC_BIT(12)
+#define NPU2_CHECKSTOP_REG0_CTL_ARRAY_CE PPC_BIT(13)
+#define NPU2_CHECKSTOP_REG0_CTL_PBUS_RECOV_ERR PPC_BIT(14)
+#define NPU2_CHECKSTOP_REG0_CTL_REG_RING_ERR PPC_BIT(15)
+#define NPU2_CHECKSTOP_REG0_CTL_MMIO_ST_DATA_UE PPC_BIT(16)
+#define NPU2_CHECKSTOP_REG0_CTL_PEF PPC_BIT(17)
+#define NPU2_CHECKSTOP_REG0_CTL_NVL_CFG_ERR PPC_BIT(18)
+#define NPU2_CHECKSTOP_REG0_CTL_NVL_FATAL_ERR PPC_BIT(19)
+#define NPU2_CHECKSTOP_REG0_RESERVED_1 PPC_BIT(20)
+#define NPU2_CHECKSTOP_REG0_CTL_ARRAY_UE PPC_BIT(21)
+#define NPU2_CHECKSTOP_REG0_CTL_PBUS_PERR PPC_BIT(22)
+#define NPU2_CHECKSTOP_REG0_CTL_PBUS_FATAL_ERR PPC_BIT(23)
+#define NPU2_CHECKSTOP_REG0_CTL_PBUS_CONFIG_ERR PPC_BIT(24)
+#define NPU2_CHECKSTOP_REG0_CTL_FWD_PROGRESS_ERR PPC_BIT(25)
+#define NPU2_CHECKSTOP_REG0_CTL_LOGIC_ERR PPC_BIT(26)
+#define NPU2_CHECKSTOP_REG0_DAT_DATA_BE_UE PPC_BIT(29)
+#define NPU2_CHECKSTOP_REG0_DAT_DATA_BE_CE PPC_BIT(30)
+#define NPU2_CHECKSTOP_REG0_DAT_DATA_BE_PERR PPC_BIT(31)
+#define NPU2_CHECKSTOP_REG0_DAT_CREG_PERR PPC_BIT(32)
+#define NPU2_CHECKSTOP_REG0_DAT_RTAG_PERR PPC_BIT(33)
+#define NPU2_CHECKSTOP_REG0_DAT_STATE_PERR PPC_BIT(34)
+#define NPU2_CHECKSTOP_REG0_DAT_LOGIC_ERR PPC_BIT(35)
+#define NPU2_CHECKSTOP_REG0_DAT_DATA_BE_SUE PPC_BIT(36)
+#define NPU2_CHECKSTOP_REG0_DAT_PBRX_SUE PPC_BIT(37)
+#define NPU2_CHECKSTOP_REG0_XTS_INT PPC_BIT(40)
+#define NPU2_CHECKSTOP_REG0_XTS_SRAM_CE PPC_BIT(41)
+#define NPU2_CHECKSTOP_REG0_XTS_SRAM_UE PPC_BIT(42)
+#define NPU2_CHECKSTOP_REG0_XTS_PROTOCOL_CE PPC_BIT(43)
+#define NPU2_CHECKSTOP_REG0_XTS_PROTOCOL_UE PPC_BIT(44)
+#define NPU2_CHECKSTOP_REG0_XTS_PBUS_PROTOCOL PPC_BIT(45)
+
+#define NPU2_CHECKSTOP_REG1_NDL_BRK0_STALL PPC_BIT(0)
+#define NPU2_CHECKSTOP_REG1_NDL_BRK0_NOSTALL PPC_BIT(1)
+#define NPU2_CHECKSTOP_REG1_NDL_BRK1_STALL PPC_BIT(2)
+#define NPU2_CHECKSTOP_REG1_NDL_BRK1_NOSTALL PPC_BIT(3)
+#define NPU2_CHECKSTOP_REG1_NDL_BRK2_STALL PPC_BIT(4)
+#define NPU2_CHECKSTOP_REG1_NDL_BRK2_NOSTALL PPC_BIT(5)
+#define NPU2_CHECKSTOP_REG1_NDL_BRK3_STALL PPC_BIT(6)
+#define NPU2_CHECKSTOP_REG1_NDL_BRK3_NOSTALL PPC_BIT(7)
+#define NPU2_CHECKSTOP_REG1_NDL_BRK4_STALL PPC_BIT(8)
+#define NPU2_CHECKSTOP_REG1_NDL_BRK4_NOSTALL PPC_BIT(9)
+#define NPU2_CHECKSTOP_REG1_NDL_BRK5_STALL PPC_BIT(10)
+#define NPU2_CHECKSTOP_REG1_NDL_BRK5_NOSTALL PPC_BIT(11)
+#define NPU2_CHECKSTOP_REG1_MISC_REG_RING_ERR PPC_BIT(12)
+#define NPU2_CHECKSTOP_REG1_MISC_INT_RA_PERR PPC_BIT(13)
+#define NPU2_CHECKSTOP_REG1_MISC_DA_ADDR_PERR PPC_BIT(14)
+#define NPU2_CHECKSTOP_REG1_MISC_CTRL_PERR PPC_BIT(15)
+#define NPU2_CHECKSTOP_REG1_MISC_NMMU_ERR PPC_BIT(16)
+#define NPU2_CHECKSTOP_REG1_ATS_TVT_ENTRY_INVALID PPC_BIT(17)
+#define NPU2_CHECKSTOP_REG1_ATS_TVT_ADDR_RANGE_ERR PPC_BIT(18)
+#define NPU2_CHECKSTOP_REG1_ATS_TCE_PAGE_ACCESS_CA_ERR PPC_BIT(19)
+#define NPU2_CHECKSTOP_REG1_ATS_TCE_CACHE_MULT_HIT_ERR PPC_BIT(20)
+#define NPU2_CHECKSTOP_REG1_ATS_TCE_PAGE_ACCESS_TW_ERR PPC_BIT(21)
+#define NPU2_CHECKSTOP_REG1_ATS_TCE_REQ_TO_ERR PPC_BIT(22)
+#define NPU2_CHECKSTOP_REG1_ATS_TCD_PERR PPC_BIT(23)
+#define NPU2_CHECKSTOP_REG1_ATS_TDR_PERR PPC_BIT(24)
+#define NPU2_CHECKSTOP_REG1_ATS_AT_EA_UE PPC_BIT(25)
+#define NPU2_CHECKSTOP_REG1_ATS_AT_EA_CE PPC_BIT(26)
+#define NPU2_CHECKSTOP_REG1_ATS_AT_TDRMEM_UE PPC_BIT(27)
+#define NPU2_CHECKSTOP_REG1_ATS_AT_TDRMEM_CE PPC_BIT(28)
+#define NPU2_CHECKSTOP_REG1_ATS_AT_RSPOUT_UE PPC_BIT(29)
+#define NPU2_CHECKSTOP_REG1_ATS_AT_RSPOUT_CE PPC_BIT(30)
+#define NPU2_CHECKSTOP_REG1_ATS_TVT_PERR PPC_BIT(31)
+#define NPU2_CHECKSTOP_REG1_ATS_IODA_ADDR_PERR PPC_BIT(32)
+#define NPU2_CHECKSTOP_REG1_ATS_NPU_CTRL_PERR PPC_BIT(33)
+#define NPU2_CHECKSTOP_REG1_ATS_NPU_TOR_PERR PPC_BIT(34)
+#define NPU2_CHECKSTOP_REG1_ATS_INVAL_IODA_TBL_SEL PPC_BIT(35)
+
+#define NPU2_CHECKSTOP_REG2_XSL_MMIO_INVALIDATE_REQ_WHILE_1_INPROG PPC_BIT(36)
+#define NPU2_CHECKSTOP_REG2_XSL_UNEXPECTED_ITAG_PORT_0 PPC_BIT(37)
+#define NPU2_CHECKSTOP_REG2_XSL_UNEXPECTED_ITAG_PORT_1 PPC_BIT(38)
+#define NPU2_CHECKSTOP_REG2_XSL_UNEXPECTED_RD_PEE_COMPLETION PPC_BIT(39)
+#define NPU2_CHECKSTOP_REG2_XSL_UNEXPECTED_CO_RESP PPC_BIT(40)
+#define NPU2_CHECKSTOP_REG2_XSL_XLAT_REQ_WHILE_SPAP_INVALID PPC_BIT(41)
+#define NPU2_CHECKSTOP_REG2_XSL_INVALID_PEE PPC_BIT(42)
+#define NPU2_CHECKSTOP_REG2_XSL_BLOOM_FILTER_PROTECT_ERR PPC_BIT(43)
+#define NPU2_CHECKSTOP_REG2_XSL_CE PPC_BIT(46)
+#define NPU2_CHECKSTOP_REG2_XSL_UE PPC_BIT(47)
+#define NPU2_CHECKSTOP_REG2_XSL_SLBI_TLBI_BUFF_OVERFLOW PPC_BIT(48)
+#define NPU2_CHECKSTOP_REG2_XSL_SBE_CORR_ERR_PB_CHKOUT_RSP_DATA PPC_BIT(49)
+#define NPU2_CHECKSTOP_REG2_XSL_UE_PB_CHKOUT_RSP_DATA PPC_BIT(50)
+#define NPU2_CHECKSTOP_REG2_XSL_SUE_PB_CHKOUT_RSP_DATA PPC_BIT(51)
+
struct OpalHMIEvent {
uint8_t version; /* 0x00 */
uint8_t severity; /* 0x01 */