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| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2017-11-01 16:59:43 +1100 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-11-09 16:55:22 -0600 |
| commit | 484d26fd6e65b00f746f852bccb460fef7b695e0 (patch) | |
| tree | 58de4ef9e86ca646f8184f1d21f7f1706036be96 /include | |
| parent | a05054c53a37850a2118d01fcf6669ebb10d1a33 (diff) | |
| download | skiboot-484d26fd6e65b00f746f852bccb460fef7b695e0.zip skiboot-484d26fd6e65b00f746f852bccb460fef7b695e0.tar.gz skiboot-484d26fd6e65b00f746f852bccb460fef7b695e0.tar.bz2 | |
xive: Update inits for DD2.0
This updates some inits based on information from the HW
designers. This includes enabling some new DD2.0 features
that we don't yet exploit.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/xive.h | 25 |
1 files changed, 20 insertions, 5 deletions
diff --git a/include/xive.h b/include/xive.h index 70f6499..63ee77b 100644 --- a/include/xive.h +++ b/include/xive.h @@ -25,6 +25,7 @@ #define CQ_SWI_RSP 0x048 #define X_CQ_CFG_PB_GEN 0x0a #define CQ_CFG_PB_GEN 0x050 +#define CQ_INT_ADDR_OPT PPC_BITMASK(14,15) #define X_CQ_IC_BAR 0x10 #define X_CQ_MSGSND 0x0b #define CQ_MSGSND 0x058 @@ -75,10 +76,15 @@ #define PC_TCTXT_CFG 0x400 #define PC_TCTXT_CFG_BLKGRP_EN PPC_BIT(0) #define PC_TCTXT_CFG_TARGET_EN PPC_BIT(1) +#define PC_TCTXT_CFG_LGS_EN PPC_BIT(2) #define PC_TCTXT_CFG_STORE_ACK PPC_BIT(3) #define PC_TCTXT_CFG_HARD_CHIPID_BLK PPC_BIT(8) #define PC_TCTXT_CHIPID_OVERRIDE PPC_BIT(9) #define PC_TCTXT_CHIPID PPC_BITMASK(12,15) +#define PC_TCTXT_INIT_AGE PPC_BITMASK(30,31) +#define X_PC_TCTXT_TRACK 0x101 +#define PC_TCTXT_TRACK 0x408 +#define PC_TCTXT_TRACK_EN PPC_BIT(0) #define X_PC_TCTXT_INDIR0 0x104 #define PC_TCTXT_INDIR0 0x420 #define PC_TCTXT_INDIR_VALID PPC_BIT(0) @@ -174,6 +180,9 @@ #define VC_IRQ_CONFIG_CASCADE2 0x858 #define VC_IRQ_CONFIG_REDIST 0x860 #define VC_IRQ_CONFIG_IPI_CASC 0x868 +#define X_VC_AIB_TX_ORDER_TAG2 0x22d +#define VC_AIB_TX_ORDER_TAG2_REL_TF PPC_BIT(20) +#define VC_AIB_TX_ORDER_TAG2 0x890 #define X_VC_AT_MACRO_KILL 0x23e #define VC_AT_MACRO_KILL 0x8b0 #define X_VC_AT_MACRO_KILL_MASK 0x23f @@ -196,11 +205,17 @@ #define X_VC_EQC_CWATCH_SPEC 0x215 #define VC_EQC_CONFIG 0x920 #define X_VC_EQC_CONFIG 0x214 -#define VC_EQC_CONF_SYNC_IPI PPC_BIT(32) -#define VC_EQC_CONF_SYNC_HW PPC_BIT(33) -#define VC_EQC_CONF_SYNC_ESC1 PPC_BIT(34) -#define VC_EQC_CONF_SYNC_ESC2 PPC_BIT(35) -#define VC_EQC_CONF_SYNC_REDI PPC_BIT(36) +#define VC_EQC_CONF_SYNC_IPI PPC_BIT(32) +#define VC_EQC_CONF_SYNC_HW PPC_BIT(33) +#define VC_EQC_CONF_SYNC_ESC1 PPC_BIT(34) +#define VC_EQC_CONF_SYNC_ESC2 PPC_BIT(35) +#define VC_EQC_CONF_SYNC_REDI PPC_BIT(36) +#define VC_EQC_CONF_EQP_INTERLEAVE PPC_BIT(38) +#define VC_EQC_CONF_ENABLE_END_s_BIT PPC_BIT(39) +#define VC_EQC_CONF_ENABLE_END_u_BIT PPC_BIT(40) +#define VC_EQC_CONF_ENABLE_END_c_BIT PPC_BIT(41) +#define VC_EQC_CONF_ENABLE_MORE_QSZ PPC_BIT(42) +#define VC_EQC_CONF_SKIP_ESCALATE PPC_BIT(43) #define VC_EQC_CWATCH_SPEC 0x928 #define VC_EQC_CWATCH_CONFLICT PPC_BIT(0) #define VC_EQC_CWATCH_FULL PPC_BIT(8) |