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| author | Christophe Lombard <clombard@linux.vnet.ibm.com> | 2021-10-14 17:56:54 +0200 |
|---|---|---|
| committer | Vasant Hegde <hegdevasant@linux.vnet.ibm.com> | 2021-10-19 12:26:01 +0530 |
| commit | 882e867012a8c4af8a7bbd42b93816b2a2f3b827 (patch) | |
| tree | ce5e90dbd3c61bcacc0b2f9476c14638d625b27f /include | |
| parent | 8baea29fdeaa5eab26c1ca6e3b88e18a3387be96 (diff) | |
| download | skiboot-882e867012a8c4af8a7bbd42b93816b2a2f3b827.zip skiboot-882e867012a8c4af8a7bbd42b93816b2a2f3b827.tar.gz skiboot-882e867012a8c4af8a7bbd42b93816b2a2f3b827.tar.bz2 | |
pau: create phb
Implement the necessary operations for the OpenCAPI PHB type and
inform the device-tree properties associated.
The OpenCapi PCI config Addr/Data registers are reachable through
the Generation-ID Registers MMIO BARS.
The Config Address and Data registers are located at the following offsets
from the AFU Config BAR plus 320 KB.
• Config Address for Brick 0 – Offset 0
• Config Data for Brick 0 – Offsets:
◦ 128 – 4-byte config register
• Config Address for Brick 1 – Offset 256
• Config Data for Brick 1 – Offsets:
◦ 384 – 4-byte config register
Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/pau-regs.h | 8 | ||||
| -rw-r--r-- | include/pau.h | 13 | ||||
| -rw-r--r-- | include/pci.h | 1 |
3 files changed, 22 insertions, 0 deletions
diff --git a/include/pau-regs.h b/include/pau-regs.h index afe6f95..5779692 100644 --- a/include/pau-regs.h +++ b/include/pau-regs.h @@ -52,5 +52,13 @@ #define PAU_CTL_MISC_MMIOPA_CONFIG(brk) (PAU_BLOCK_CQ_CTL + 0x098 + (brk) * 8) #define PAU_CTL_MISC_MMIOPA_CONFIG_BAR_ADDR PPC_BITMASK(1, 35) #define PAU_CTL_MISC_MMIOPA_CONFIG_BAR_SIZE PPC_BITMASK(39, 43) +#define PAU_CTL_MISC_CFG_ADDR(brk) (PAU_BLOCK_CQ_CTL + 0x250 + (brk) * 8) +#define PAU_CTL_MISC_CFG_ADDR_ENABLE PPC_BIT(0) +#define PAU_CTL_MISC_CFG_ADDR_STATUS PPC_BITMASK(1, 3) +#define PAU_CTL_MISC_CFG_ADDR_BUS_NBR PPC_BITMASK(4, 11) +#define PAU_CTL_MISC_CFG_ADDR_DEVICE_NBR PPC_BITMASK(12, 16) +#define PAU_CTL_MISC_CFG_ADDR_FUNCTION_NBR PPC_BITMASK(17, 19) +#define PAU_CTL_MISC_CFG_ADDR_REGISTER_NBR PPC_BITMASK(20, 31) +#define PAU_CTL_MISC_CFG_ADDR_TYPE PPC_BIT(32) #endif /* __PAU_REGS_H */ diff --git a/include/pau.h b/include/pau.h index be8ed26..fdf85f8 100644 --- a/include/pau.h +++ b/include/pau.h @@ -8,6 +8,7 @@ #include <io.h> #include <pci.h> #include <xscom.h> +#include <phb4.h> #include <pau-regs.h> #define PAU_NBR 6 @@ -30,6 +31,7 @@ struct pau_dev { enum pau_dev_type type; uint32_t index; struct dt_node *dn; + struct phb phb; struct pau_bar ntl_bar; struct pau_bar genid_bar; @@ -86,6 +88,12 @@ static inline uint32_t pau_dev_index(struct pau_dev *dev, int links) return dev->pau->index * links + dev->index; } +static inline struct pau_dev *pau_phb_to_opencapi_dev(struct phb *phb) +{ + assert(phb->phb_type == phb_type_pau_opencapi); + return container_of(phb, struct pau_dev, phb); +} + struct pau_dev *pau_next_dev(struct pau *pau, struct pau_dev *dev, enum pau_dev_type type); @@ -105,6 +113,11 @@ static inline int pau_get_phb_index(unsigned int pau_index, return PAU_PHB_INDEX_BASE + pau_index * 2 + link_index; } +static inline int pau_get_opal_id(unsigned int chip_id, unsigned int index) +{ + return phb4_get_opal_id(chip_id, index); +} + /* * We use the indirect method because it uses the same addresses as * the MMIO offsets (PAU RING) diff --git a/include/pci.h b/include/pci.h index 8d46721..caae744 100644 --- a/include/pci.h +++ b/include/pci.h @@ -352,6 +352,7 @@ enum phb_type { phb_type_pcie_v4, phb_type_npu_v2, phb_type_npu_v2_opencapi, + phb_type_pau_opencapi, }; /* Generic PCI NVRAM flags */ |