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author | Oliver O'Halloran <oohall@gmail.com> | 2019-06-26 09:48:33 +1000 |
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committer | Stewart Smith <stewart@linux.ibm.com> | 2019-06-27 11:35:22 +1000 |
commit | 4a3ce90df510768171bfdd4bfca524510c86963e (patch) | |
tree | d785ad8ab617fba9c7e095df244e8f6243911ebf /include | |
parent | 4025c84b4582d7194ffa93cbcd27bf84140d3337 (diff) | |
download | skiboot-4a3ce90df510768171bfdd4bfca524510c86963e.zip skiboot-4a3ce90df510768171bfdd4bfca524510c86963e.tar.gz skiboot-4a3ce90df510768171bfdd4bfca524510c86963e.tar.bz2 |
pci: Make the pci-eeh-verbose nvram option generic
We currently have the "pci-eeh-verbose" NVRAM flag that causes phb4 to
print a register dump when it detects the PHB has been fenced. This is
useful for debugging most EEH issues since the kernel may not be ready
to handle EEH events when the problem is first detected.
There's no real reason this needs to be specific to PHB4 so this patch
moves the nvram flag handling into the generic init path (along with the
pcie_max_link_speed flag) so we can add a similar function for PHB3.
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
Diffstat (limited to 'include')
-rw-r--r-- | include/pci.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/pci.h b/include/pci.h index 2b7a3c2..c10d794 100644 --- a/include/pci.h +++ b/include/pci.h @@ -368,6 +368,9 @@ enum phb_type { phb_type_npu_v2_opencapi, }; + +extern bool verbose_eeh; + struct phb { struct dt_node *dt_node; int opal_id; |