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| author | Reza Arbab <arbab@linux.ibm.com> | 2019-08-05 15:33:26 -0500 |
|---|---|---|
| committer | Oliver O'Halloran <oohall@gmail.com> | 2019-08-16 15:51:55 +1000 |
| commit | 3e334fbb85417da0dae045fcec350efc3dae206b (patch) | |
| tree | 99e79fac269c46048f467a45e32799ece1f91110 /include | |
| parent | e4e2aa9cc2cbaab9c6c0ee3a1f4e36292128762a (diff) | |
| download | skiboot-3e334fbb85417da0dae045fcec350efc3dae206b.zip skiboot-3e334fbb85417da0dae045fcec350efc3dae206b.tar.gz skiboot-3e334fbb85417da0dae045fcec350efc3dae206b.tar.bz2 | |
npu3: Rename NPU3_SM_MISC_CFGn register macros
The SM blocks have multiple MISC_CFG registers. For example, there are
both CS.SM0.MCP.MISC.CONFIG0 and CS.SM0.SNP.MISC.CONFIG0. Rename our
macro for the former to more clearly reflect this and avoid a clash when
the latter is added.
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
Reviewed-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/npu3-regs.h | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/include/npu3-regs.h b/include/npu3-regs.h index 2e1dc39..c0c7eab 100644 --- a/include/npu3-regs.h +++ b/include/npu3-regs.h @@ -86,13 +86,13 @@ * Definitions here use NPU3_BLOCK_CQ_SM(0), but when npu3_write() is given * one of these, it will do corresponding writes to every CQ_SM block. */ -#define NPU3_SM_MISC_CFG0 (NPU3_BLOCK_CQ_SM(0) + 0x000) -#define NPU3_SM_MISC_CFG0_ENABLE_PBUS PPC_BIT(26) -#define NPU3_SM_MISC_CFG0_ENABLE_SNARF_CPM PPC_BIT(27) -#define NPU3_SM_MISC_CFG0_OCAPI_MODE PPC_BITMASK(44, 48) -#define NPU3_SM_MISC_CFG0_NVLINK_MODE PPC_BITMASK(49, 53) -#define NPU3_SM_MISC_CFG1 (NPU3_BLOCK_CQ_SM(0) + 0x008) -#define NPU3_SM_MISC_CFG2 (NPU3_BLOCK_CQ_SM(0) + 0x0f0) +#define NPU3_MCP_MISC_CFG0 (NPU3_BLOCK_CQ_SM(0) + 0x000) +#define NPU3_MCP_MISC_CFG0_ENABLE_PBUS PPC_BIT(26) +#define NPU3_MCP_MISC_CFG0_ENABLE_SNARF_CPM PPC_BIT(27) +#define NPU3_MCP_MISC_CFG0_OCAPI_MODE PPC_BITMASK(44, 48) +#define NPU3_MCP_MISC_CFG0_NVLINK_MODE PPC_BITMASK(49, 53) +#define NPU3_MCP_MISC_CFG1 (NPU3_BLOCK_CQ_SM(0) + 0x008) +#define NPU3_MCP_MISC_CFG2 (NPU3_BLOCK_CQ_SM(0) + 0x0f0) #define NPU3_GPU_MEM_BAR(brk) (NPU3_BLOCK_CQ_SM(0) + 0x190 + (brk) * 8) #define NPU3_GPU_MEM_BAR_ENABLE PPC_BIT(0) #define NPU3_GPU_MEM_BAR_ADDR_MASK PPC_BITMASK(1, 35) |