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| author | Vasant Hegde <hegdevasant@linux.vnet.ibm.com> | 2019-07-12 16:47:52 +0530 |
|---|---|---|
| committer | Oliver O'Halloran <oohall@gmail.com> | 2019-08-15 17:53:43 +1000 |
| commit | 0a17e674616413b7a3182643cfa0fda292141bb1 (patch) | |
| tree | 670a972e93540e6f7f079109c12b3bb972e081a7 /include | |
| parent | 166eda4e0aa886658280956b479a92bfc0d1c572 (diff) | |
| download | skiboot-0a17e674616413b7a3182643cfa0fda292141bb1.zip skiboot-0a17e674616413b7a3182643cfa0fda292141bb1.tar.gz skiboot-0a17e674616413b7a3182643cfa0fda292141bb1.tar.bz2 | |
MPIPL: Add support to trigger MPIPL on BMC system
On FSP based system we call 'attn' instruction. FSP detects attention and
initiates memory preserving IPL. On BMC system we have to call SBE S0
interrupt to initiate memory preserving IPL.
This patch adds support to call SBE S0 interrupt in assert path.
Sequence :
- S0 interrupt on secondary chip SBE
- S0 interrupt on primary chip SBE
Note that this is hooked to ipmi_terminate path. We have HDAT flag for MPIPL
support. If MPIPL is not supported then we don't create 'ibm,opal/dump' node
and we will fall back to existing termination flow.
Finally we want to log error log to BMC before triggerring MPIPL. Hence this
patch re-organizes ipmi_terminate() such that we call ipmi_log_terminate_event()
before triggering MPIPL.
Note:
- At present we do not have a proper way to detect SBE is alive or not.
So we wait for predefined time and then call normal reboot.
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
[oliver: rebased]
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/sbe-p9.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/include/sbe-p9.h b/include/sbe-p9.h index 768d1a5..ceb0755 100644 --- a/include/sbe-p9.h +++ b/include/sbe-p9.h @@ -90,6 +90,13 @@ #define SBE_HOST_TIMER_EXPIRY PPC_BIT(14) #define SBE_HOST_RESPONSE_MASK (PPC_BITMASK(0, 4) | SBE_HOST_TIMER_EXPIRY) +/* SBE Control Register */ +#define SBE_CONTROL_REG_RW 0x00050008 + +/* SBE interrupt s0/s1 bits */ +#define SBE_CONTROL_REG_S0 PPC_BIT(14) +#define SBE_CONTROL_REG_S1 PPC_BIT(15) + /* SBE Target Type */ #define SBE_TARGET_TYPE_PROC 0x00 #define SBE_TARGET_TYPE_EX 0x01 @@ -230,4 +237,7 @@ extern void p9_sbe_update_timer_expiry(uint64_t new_target); /* Send skiboot relocated base address to SBE */ extern void p9_sbe_send_relocated_base(uint64_t reloc_base); +/* Terminate and trigger MPIPL */ +extern void p9_sbe_terminate(void); + #endif /* __SBE_P9_H */ |