Drop support for p5ioc2

p5ioc2 is used by approximately 2 machines in the world, and has never
ever been a supported configuration.

Not only is the code virtually unused and very tricky to test, but
keeping it around is making life unnecessarily difficult:

 - It's more complexity to manage for things such as PCI slot support
 - It's more code for static analysis to cover, which means more time
   fixing bugs that affect no-one.
 - It's bloating every single install of skiboot for no benefit.
 - It's reducing coverage stats, which is sad.

Drop p5ioc2.

Signed-off-by: Daniel Axtens <dja@axtens.net>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>

4 files changed, 0 insertions, 423 deletions

diff --git a/include/cec.h b/include/cec.h
index 87cdc0e..97da17a 100644
--- a/include/cec.h
+++ b/include/cec.h
@@ -26,10 +26,6 @@
 struct io_hub;
 
 struct io_hub_ops {
-	/* OPAL_PCI_SET_HUB_TCE_MEMORY (p5ioc2 only) */
-	int64_t (*set_tce_mem)(struct io_hub *hub, uint64_t address,
-				   uint64_t size);
-
 	/* OPAL_PCI_GET_HUB_DIAG_DATA */
 	int64_t (*get_diag_data)(struct io_hub *hub, void *diag_buffer,
 				 uint64_t diag_buffer_len);
diff --git a/include/p5ioc2-regs.h b/include/p5ioc2-regs.h
deleted file mode 100644
index 1628f7a..0000000
--- a/include/p5ioc2-regs.h
+++ /dev/null
@@ -1,234 +0,0 @@
-/* Copyright 2013-2014 IBM Corp.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * 	http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
- * implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __P5IOC2_REGS_H
-#define __P5IOC2_REGS_H
-
-/*
- * IO HUB registers
- *
- * Most (all) of those registers support an AND access
- * at address + 0x1000 and an OR access at address + 0x2000
- */
-#define P5IOC2_REG_AND		0x1000
-#define P5IOC2_REG_OR		0x2000
-
-/* Internal BARs */
-#define P5IOC2_BAR0		0x0100
-#define P5IOC2_BAR1		0x0108
-#define P5IOC2_BAR2		0x0110
-#define P5IOC2_BAR3		0x0118
-#define P5IOC2_BAR4		0x0120
-#define P5IOC2_BAR5		0x0128
-#define P5IOC2_BAR6		0x0130
-#define P5IOC2_BAR7		0x0138
-#define P5IOC2_BARM0		0x0180
-#define P5IOC2_BARM1		0x0188
-#define P5IOC2_BARM2		0x0190
-#define P5IOC2_BARM3		0x0198
-#define P5IOC2_BARM4		0x01a0
-#define P5IOC2_BARM5		0x01a8
-#define P5IOC2_BARM6		0x01b0
-#define P5IOC2_BARM7		0x01b8
-#define P5IOC2_BAR(n)		(0x100 + ((n) << 3))
-#define P5IOC2_BARM(n)		(0x180 + ((n) << 3))
-
-/* Routing table */
-#define P5IOC2_TxRTE(x,n)	(0x200 + ((x) << 7) + ((n) << 3))
-#define   P5IOC2_TxRTE_VALID	PPC_BIT(47)
-
-/* BUID routing table */
-#define P5IOC2_BUIDRTE(n)	(0x600 + ((n) << 3))
-#define   P5IOC2_BUIDRTE_VALID	PPC_BIT(47)
-#define   P5IOC2_BUIDRTE_RR_EOI	PPC_BIT(48)
-#define   P5IOC2_BUIDRTE_RR_RET	PPC_BIT(49)
-
-/* Others */
-#define P5IOC2_FIRMC		0x0008  /* FIR Mask Checkstop */
-#define P5IOC2_CTL		0x0030	/* Control register part 1 */
-#define P5IOC2_CTL2		0x00c8	/* Control register part 2 */
-#define P5IOC2_DIRA		0x0090  /* Cache dir. address */
-#define P5IOC2_DIRD		0x0098  /* Cache dir. data */
-#define P5IOC2_IBASE		0x0048	/* Interrupt base address */
-#define P5IOC2_IRBM		0x00d8  /* Interrupt re-issue broadcast mask */
-#define P5IOC2_SID		0x0038  /* P5IOC2 ID register */
-#define   P5IOC2_SID_BUID_BASE	PPC_BITMASK(14,22)
-#define   P5IOC2_SID_BUID_MASK	PPC_BITMASK(27,30)
-#define P5IOC2_SBUID 		0x00f8  /* P5IOC2 HUB BUID */
-
-/* XIPM area */
-#define P5IOC2_BUCO		0x40008
-#define P5IOC2_MIIP		0x40000
-#define P5IOC2_XINM		0x40010
-
-/* Xin/Xout area */
-#define P5IOC2_XIXO		0xf0030
-#define   P5IOC2_XIXO_ENH_TCE	PPC_BIT(0)
-
-/*
- * Calgary registers
- *
- * CA0 is PCI-X and CA1 is PCIE, though the type can be discovered
- * from registers so we'll simply let it do so
- */
-
-#define CA_CCR				0x108
-#define CA_DEVBUID			0x118
-#define   CA_DEVBUID_MASK		PPC_BITMASK32(7,15)
-#define CA_TAR0				0x580
-#define   CA_TAR_HUBID			PPC_BITMASK(0,5)
-#define   CA_TAR_ALTHUBID		PPC_BITMASK(6,11)
-#define   CA_TAR_TCE_ADDR		PPC_BITMASK(16,48)
-#define   CA_TAR_VALID			PPC_BIT(60)
-#define   CA_TAR_NUM_TCE		PPC_BITMASK(61,63)
-#define CA_TAR1				0x588
-#define CA_TAR2				0x590
-#define CA_TAR3				0x598
-#define CA_TARn(n)			(0x580 + ((n) << 3))
-
-#define CA_PHBID0			0x650
-#define   CA_PHBID_PHB_ENABLE		PPC_BIT32(0)
-#define   CA_PHBID_ADDRSPACE_ENABLE	PPC_BIT32(1)
-#define   CA_PHBID_PHB_TYPE		PPC_BITMASK32(4,7)
-#define     CA_PHBTYPE_PCIX1_0	0
-#define     CA_PHBTYPE_PCIX2_0	1
-#define     CA_PHBTYPE_PCIE_G1	4
-#define     CA_PHBTYPE_PCIE_G2	5
-/* PCI-X bits */
-#define   CA_PHBID_XMODE_EMBEDDED	PPC_BIT32(8)
-#define   CA_PHBID_XBUS_64BIT		PPC_BIT32(9)
-#define   CA_PHBID_XBUS_266MHZ		PPC_BIT32(10)
-/* PCI-E bits */
-#define   CA_PHBID_EWIDTH		PPC_BITMASK32(8,10)
-#define     CA_PHB_EWIDTH_X4	0
-#define     CA_PHB_EWIDTH_X8	1
-#define     CA_PHB_EWIDTH_X16	2
-#define CA_PHBID1			0x658
-#define CA_PHBID2			0x660
-#define CA_PHBID3			0x668
-#define CA_PHBIDn(n)			(0x650 + ((n) << 3))
-
-/* PHB n reg base inside CA */
-#define CA_PHBn_REGS(n)			(0x8000 + ((n) << 12))
-
-/*
- * P5IOC2 PHB registers
- */
-#define CAP_BUID			0x100
-#define   CAP_BUID_MASK			PPC_BITMASK32(7,15)
-#define CAP_MSIBASE			0x108 /* Undocumented ! */
-#define CAP_DMACSR			0x110
-#define CAP_PLSSR			0x120
-#define CAP_PCADR			0x140
-#define   CAP_PCADR_ENABLE		PPC_BIT32(0)
-#define   CAP_PCADR_FUNC		PPC_BITMASK32(21,23)
-#define   CAP_PCADR_BDFN		PPC_BITMASK32(8,23) /* bus,dev,func */
-#define   CAP_PCADR_EXTOFF		PPC_BITMASK32(4,7)
-#define CAP_PCDAT			0x130
-#define CAP_PCFGRW			0x160
-#define   CAP_PCFGRW_ERR_RECOV_EN	PPC_BIT32(1)
-#define   CAP_PCFGRW_TCE_EN		PPC_BIT32(2)
-#define   CAP_PCFGRW_FREEZE_EN		PPC_BIT32(3)
-#define   CAP_PCFGRW_MMIO_FROZEN	PPC_BIT32(4)
-#define   CAP_PCFGRW_DMA_FROZEN		PPC_BIT32(5)
-#define   CAP_PCFGRW_ENHANCED_CFG_EN	PPC_BIT32(6)
-#define   CAP_PCFGRW_DAC_DISABLE	PPC_BIT32(7)
-#define   CAP_PCFGRW_2ND_MEM_SPACE_EN	PPC_BIT32(9)
-#define   CAP_PCFGRW_MASK_PLSSR_IRQ	PPC_BIT32(10)
-#define   CAP_PCFGRW_MASK_CSR_IRQ	PPC_BIT32(11)
-#define   CAP_PCFGRW_IO_SPACE_DIABLE	PPC_BIT32(12)
-#define   CAP_PCFGRW_SZ_MASK_IS_LIMIT	PPC_BIT32(13)
-#define   CAP_PCFGRW_MSI_EN		PPC_BIT32(14)
-#define CAP_IOAD_L			0x170
-#define CAP_IOAD_H			0x180
-#define CAP_MEM1_L			0x190
-#define CAP_MEM1_H			0x1a0
-#define CAP_IOSZ			0x1b0
-#define CAP_MSZ1			0x1c0
-#define CAP_MEM_ST			0x1d0
-#define CAP_IO_ST			0x1e0
-#define CAP_AER				0x200
-#define CAP_BPR				0x210
-#define CAP_CRR				0x270
-#define   CAP_CRR_RESET1		PPC_BIT32(0)
-#define   CAP_CRR_RESET2		PPC_BIT32(1)
-#define CAP_XIVR0			0x400
-#define   CAP_XIVR_PRIO			0x000000ff
-#define   CAP_XIVR_SERVER		0x0000ff00
-#define CAP_XIVRn(n)			(0x400 + ((n) << 4))
-#define CAP_MVE0			0x500
-#define   CAP_MVE_VALID			PPC_BIT32(0)
-#define   CAP_MVE_TBL_OFF		PPC_BITMASK32(13,15)
-#define   CAP_MVE_NUM_INT		PPC_BITMASK32(18,19)
-#define CAP_MVE1			0x510
-#define CAP_MODE0			0x880
-#define CAP_MODE1			0x890
-#define CAP_MODE2			0x8a0
-#define CAP_MODE3			0x8b0
-
-/*
- * SHPC Registers
- */
-#define SHPC_LOGICAL_SLOT		0xb40
-#define SHPC_LOGICAL_SLOT_STATE		0x00000003
-#define   SHPC_SLOT_STATE_POWER_ONLY	1
-#define   SHPC_SLOT_STATE_ENABLED	2
-#define   SHPC_SLOT_STATE_DISABLED	3
-#define SHPC_LOGICAL_SLOT_PRSNT		0x000000c00
-#define   SHPC_SLOT_PRSTN_7_5W		0
-#define   SHPC_SLOT_PRSTN_25W		1
-#define   SHPC_SLOT_STATE_15W		2
-#define   SHPC_SLOT_STATE_EMPTY		3
-
-/* UTL registers */
-#define UTL_SYS_BUS_CONTROL		0xc00
-#define UTL_STATUS			0xc04
-#define UTL_SYS_BUS_AGENT_STATUS	0xc08
-#define UTL_SYS_BUS_AGENT_ERR_EN	0xc0c
-#define UTL_SYS_BUS_AGENT_IRQ_EN	0xc10
-#define UTL_SYS_BUS_BURST_SZ_CONF	0xc20
-#define UTL_REVISION_ID			0xc24
-#define UTL_TX_NON_POST_DEBUG_STAT1	0xc30
-#define UTL_TX_NON_POST_DEBUG_STAT2	0xc34
-#define UTL_GBIF_READ_REQ_DEBUG		0xc38
-#define UTL_GBIF_WRITE_REQ_DEBUG	0xc3c
-#define UTL_GBIF_TX_COMP_DEBUG		0xc40
-#define UTL_GBIF_RX_COMP_DEBUG		0xc44
-#define UTL_OUT_POST_HDR_BUF_ALLOC	0xc60
-#define UTL_OUT_POST_DAT_BUF_ALLOC	0xc68
-#define UTL_IN_POST_HDR_BUF_ALLOC	0xc70
-#define UTL_IN_POST_DAT_BUF_ALLOC	0xc78
-#define UTL_OUT_NP_BUF_ALLOC		0xc80
-#define UTL_IN_NP_BUF_ALLOC		0xc88
-#define UTL_PCIE_TAGS_ALLOC		0xc90
-#define UTL_GBIF_READ_TAGS_ALLOC	0xc98
-#define UTL_PCIE_PORT_CONTROL		0xca0
-#define UTL_PCIE_PORT_STATUS		0xca4
-#define UTL_PCIE_PORT_ERR_EN		0xca8
-#define UTL_PCIE_PORT_IRQ_EN		0xcac
-#define UTL_RC_STATUS			0xcb0
-#define UTL_RC_ERR_EN			0xcb4
-#define UTL_RC_IRQ_EN			0xcb8
-#define UTL_PCI_PM_CONTROL		0xcc8
-#define UTL_PCIE_PORT_ID		0xccc
-#define UTL_TLP_DEBUG			0xcd0
-#define UTL_VC_CTL_DEBUG		0xcd4
-#define UTL_NP_BUFFER_DEBUG		0xcd8
-#define UTL_POSTED_BUFFER_DEBUG		0xcdc
-#define UTL_TX_FIFO_DEBUG		0xce0
-#define UTL_TLP_COMPL_DEBUG		0xce4
-
-#endif /* __P5IOC2_REGS_H */
diff --git a/include/p5ioc2.h b/include/p5ioc2.h
deleted file mode 100644
index fb9ed1b..0000000
--- a/include/p5ioc2.h
+++ /dev/null
@@ -1,184 +0,0 @@
-/* Copyright 2013-2014 IBM Corp.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * 	http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
- * implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __P5IOC2_H
-#define __P5IOC2_H
-
-#include <stdint.h>
-#include <cec.h>
-#include <io.h>
-#include <cec.h>
-#include <pci.h>
-#include <lock.h>
-#include <device.h>
-
-#include <ccan/container_of/container_of.h>
-
-/*
- * Various definitions which are the result of various
- * things we have hard wired (routing etc...)
- */
-
-/* It looks like our registers are at an offset from GX BAR 0 ... */
-#define P5IOC2_REGS_OFFSET		0x01F00000
-
-#define P5IOC2_CA0_REG_OFFSET		0	   /* From BAR6, R0 */
-#define P5IOC2_CA1_REG_OFFSET		0x01000000 /* From BAR6, R1 */
-#define P5IOC2_CA0_MM_OFFSET		0	   /* From BAR0, R0 and 1 */
-#define P5IOC2_CA1_MM_OFFSET	        0x400000000ul /* From BAR0, R1 and 2 */
-#define P5IOC2_CA_PHB_COUNT		4
-#define P5IOC2_CA0_RIO_ID		2
-#define P5IOC2_CA1_RIO_ID		3
-#define P5IOC2_CA0_BUID			0x10
-#define P5IOC2_CA1_BUID			0x20
-
-/*
- * Our memory space is slightly different than pHyp
- * (or even BML). We do as follow:
- *
- *  - IO space is in the Calgary MMIO, at (phb_index +1) * 1M
- *    (pHyp seems to mangle the IO space location) and is always
- *    1M in size mapping to PCI 0
- *
- * -  Memory space is in the BAR0 mapped region. Each PHB gets
- *    allocated a 4G window at base + (phb_index * 4G). It uses
- *    a portion of that space based on the chosen size of the
- *    MMIO space, typically 2G.
- */
-#define MM_WINDOW_SIZE	0x100000000ul
-#define MM_PCI_START	 0x80000000
-#define MM_PCI_SIZE	 0x80000000
-#define IO_PCI_START	 0x00000000
-#define IO_PCI_SIZE	 0x00100000
-
-/*
- * CAn interrupts
- *
- * Within Calgary BUID space
- */
-#define P5IOC2_CA_HOST_IRQ		0
-#define P5IOC2_CA_SPCN_IRQ		1
-#define P5IOC2_CA_PERF_IRQ		2
-
-/*
- * The PHB states are similar to P7IOC, see the explanation
- * in p7ioc.h
- */
-enum p5ioc2_phb_state {
-	/* First init state */
-	P5IOC2_PHB_STATE_UNINITIALIZED,
-
-	/* During PHB HW inits */
-	P5IOC2_PHB_STATE_INITIALIZING,
-
-	/* Set if the PHB is for some reason unusable */
-	P5IOC2_PHB_STATE_BROKEN,
-
-	/* Normal PHB functional state */
-	P5IOC2_PHB_STATE_FUNCTIONAL,
-};
-
-/*
- * Structure for a PHB
- */
-
-struct p5ioc2;
-
-struct p5ioc2_phb {
-	bool				active;	/* Is this PHB functional ? */
-	bool				is_pcie;
-	uint8_t				ca;	/* CA0 or CA1 */
-	uint8_t				index;	/* 0..3 index inside CA */
-	void				*ca_regs;  /* Calgary regs */
-	void				*regs;	   /* PHB regs */
-	struct lock			lock;
-	uint32_t			buid;
-	uint64_t			mm_base;
-	uint64_t			io_base;
-	int64_t				ecap;	/* cached PCI-E cap offset */
-	int64_t				aercap; /* cached AER ecap offset */
-	enum p5ioc2_phb_state		state;
-	uint64_t			delay_tgt_tb;
-	uint64_t			retries;
-	uint64_t			xive_cache[16];
-	struct p5ioc2			*ioc;
-	struct phb			phb;
-};
-
-static inline struct p5ioc2_phb *phb_to_p5ioc2_phb(struct phb *phb)
-{
-	return container_of(phb, struct p5ioc2_phb, phb);
-}
-
-extern void p5ioc2_phb_setup(struct p5ioc2 *ioc, struct p5ioc2_phb *p,
-			     uint8_t ca, uint8_t index, bool active,
-			     uint32_t buid);
-
-/*
- * State structure for P5IOC2 IO HUB
- */
-struct p5ioc2 {
-	/* Device node */
-	struct dt_node			*dt_node;
-
-	/* MMIO regs for the chip */
-	void				*regs;
-
-	/* BAR6 (matches GX BAR 1) is used for internal Calgary MMIO and
-	 * for PCI IO space.
-	 */
-	uint64_t			bar6;
-
-	/* BAR0 (matches GX BAR 2) is used for PCI memory space */
-	uint64_t			bar0;
-
-	/* Calgary 0 and 1 registers. We assume their BBAR values as such
-	 * that CA0 is at bar6 and CA1 at bar6 + 16M
-	 */
-	void*				ca0_regs;
-	void*				ca1_regs;
-
-	/* The large MM regions assigned off bar0 to CA0 and CA1 for use
-	 * by their PHBs (16G each)
-	 */
-	uint64_t			ca0_mm_region;
-	uint64_t			ca1_mm_region;
-
-	/* BUID base for the PHB. This does include the top bits
-	 * (chip, GX bus ID, etc...). This is initialized from the
-	 * SPIRA.
-	 */
-	uint32_t			buid_base;
-
-	/* TCE region set by the user */
-	uint64_t			tce_base;
-	uint64_t			tce_size;
-
-	/* Calgary 0 and 1 PHBs */
-	struct p5ioc2_phb		ca0_phbs[P5IOC2_CA_PHB_COUNT];
-	struct p5ioc2_phb		ca1_phbs[P5IOC2_CA_PHB_COUNT];
-
-	uint32_t			host_chip;
-	uint32_t			gx_bus;
-	struct io_hub			hub;
-};
-
-static inline struct p5ioc2 *iohub_to_p5ioc2(struct io_hub *hub)
-{
-	return container_of(hub, struct p5ioc2, hub);
-}
-
-#endif /* __P5IOC2_H */
diff --git a/include/skiboot.h b/include/skiboot.h
index e26ad2e..a85fafc 100644
--- a/include/skiboot.h
+++ b/include/skiboot.h
@@ -197,7 +197,6 @@ extern void init_shared_sprs(void);
 extern void init_replicated_sprs(void);
 
 /* Various probe routines, to replace with an initcall system */
-extern void probe_p5ioc2(void);
 extern void probe_p7ioc(void);
 extern void probe_phb3(void);
 extern int phb3_preload_capp_ucode(void);