diff options
| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2016-08-09 16:38:07 +1000 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2016-08-11 19:54:22 +1000 |
| commit | c28ea2f0b7d6ab1d1ada871690169b21a11aad10 (patch) | |
| tree | 05b63e7a8dc6f056d226fe966c497393a56e1a2a /include | |
| parent | 5ed551115a3ad1925c900b2e0dd7977ad1987f85 (diff) | |
| download | skiboot-c28ea2f0b7d6ab1d1ada871690169b21a11aad10.zip skiboot-c28ea2f0b7d6ab1d1ada871690169b21a11aad10.tar.gz skiboot-c28ea2f0b7d6ab1d1ada871690169b21a11aad10.tar.bz2 | |
psi: Add P9 support
This reworks interrupt handling a bit and adds support for XIVE
based interrupts and the new sources available on POWER9.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/interrupts.h | 2 | ||||
| -rw-r--r-- | include/psi.h | 39 |
2 files changed, 39 insertions, 2 deletions
diff --git a/include/interrupts.h b/include/interrupts.h index 23d785c..2f8c275 100644 --- a/include/interrupts.h +++ b/include/interrupts.h @@ -213,7 +213,7 @@ uint32_t p8_irq_to_phb(uint32_t irq); #define P8_IRQ_PSI_FSI 2 #define P8_IRQ_PSI_LPC 3 #define P8_IRQ_PSI_LOCAL_ERR 4 -#define P8_IRQ_PSI_HOST_ERR 5 +#define P8_IRQ_PSI_EXTERNAL 5 /* Used for UART */ #define P8_IRQ_PSI_IRQ_COUNT 6 /* TBD: NX, AS, ... diff --git a/include/psi.h b/include/psi.h index cb8d7ea..68e076c 100644 --- a/include/psi.h +++ b/include/psi.h @@ -106,9 +106,20 @@ #define PSIHB_IRQ_STAT_LOCAL_ERR PPC_BIT(30) #define PSIHB_IRQ_STAT_HOST_ERR PPC_BIT(31) -/* Secure version of CR for P8 (TCE enable bit) */ +/* Secure version of CR for P8 and P9 (TCE enable bit) */ #define PSIHB_PHBSCR 0x90 +/* P9 registers */ + +#define PSIHB_INTERRUPT_CONTROL 0x58 +#define PSIHB_IRQ_METHOD PPC_BIT(0) +#define PSIHB_IRQ_RESET PPC_BIT(1) +#define PSIHB_ESB_CI_BASE 0x60 +#define PSIHB_ESB_CI_VALID 1 +#define PSIHB_ESB_NOTIF_ADDR 0x68 +#define PSIHB_ESB_NOTIF_VALID 1 +#define PSIHB_IVT_OFFSET 0x70 +#define PSIHB_IVT_OFF_SHIFT 32 /* * PSI Host Bridge Registers (XSCOM) */ @@ -126,6 +137,31 @@ #define PSIHB_XSCOM_P8_HBCSR_CLR 0x13 #define PSIHB_XSCOM_P8_HBSCR_FSP_IRQ PPC_BIT(17) +#define PSIHB_XSCOM_P9_BASE 0xa +#define PSIHB_XSCOM_P9_HBBAR_EN PPC_BIT(63) +#define PSIHB_XSCOM_P9_HBCSR 0xe +#define PSIHB_XSCOM_P9_HBCSR_SET 0x12 +#define PSIHB_XSCOM_P9_HBCSR_CLR 0x13 +#define PSIHB_XSCOM_P9_HBSCR_FSP_IRQ PPC_BIT(17) + +/* P9 PSI Interrupts */ +#define P9_PSI_IRQ_PSI 0 +#define P9_PSI_IRQ_OCC 1 +#define P9_PSI_IRQ_FSI 2 +#define P9_PSI_IRQ_LPCHC 3 +#define P9_PSI_IRQ_LOCAL_ERR 4 +#define P9_PSI_IRQ_GLOBAL_ERR 5 +#define P9_PSI_IRQ_EXTERNAL 6 +#define P9_PSI_IRQ_LPC_SIRQ0 7 +#define P9_PSI_IRQ_LPC_SIRQ1 8 +#define P9_PSI_IRQ_LPC_SIRQ2 9 +#define P9_PSI_IRQ_LPC_SIRQ3 10 +#define P9_PSI_IRQ_SBE_I2C 11 +#define P9_PSI_IRQ_DIO 12 +#define P9_PSI_IRQ_PSU 13 +#define P9_PSI_NUM_IRQS 16 + + /* * Layout of the PSI DMA address space @@ -205,6 +241,7 @@ struct psi { struct list_node list; uint64_t xscom_base; void *regs; + void *esb_mmio; unsigned int chip_id; unsigned int interrupt; bool working; |